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Wed, 25 Aug 2021 20:10:07 -0500 From: Aurabindo Pillai To: CC: , , , , Daniel Wheeler Subject: [PATCH 4/4] drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box Date: Wed, 25 Aug 2021 21:10:02 -0400 Message-ID: <20210826011002.425361-4-aurabindo.pillai@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210826011002.425361-1-aurabindo.pillai@amd.com> References: <20210826011002.425361-1-aurabindo.pillai@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ef0aa02f-b3db-4f09-27ad-08d9682e3fbd X-MS-TrafficTypeDiagnostic: MWHPR12MB1133: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7nOlJIv4W1vsCzOxWRIwuKUxmPZTxUdNvVWhfIh2HxCjo776BEu0Wkq57sPNwNB1CuJQMBm3vWUINmElbHLcJeTeRDrYxXXrcYvtuPziP8C+B7RqH3WyOWGSIeCwd2boYTKBnfvMOoFaeqgPQ/epJ4W+6rNLd2OwVMJ+rndImjlN3IdXj8jVLs1TxLtSI6l8YJdRGuYw1KPsizcop34IIXVuUyv1QW1Q0c8kJ7fhRVZgjIl90c0kRCfilqJYMYGKG2sCzQEh9/pJ8MEK7TKynhQXxRaeLRXvxr/rBJ/6qLGSY0+6yMqUpmz9C9Jw92vTdGHD88tFUe/iMlibg+1ZIcD/oMB1EFqiU778FwzIEhNxHAi+cmD6xW0bf49H4Pzjc8PY7FGVoXEAENtJMKuiwsWgne1kzuxv6ti1edZSEuyDXy1ZnPT85VEzPqMYPGz5e39qu6wZLcm6tP07smvqklEaQkKqqGJx86LwVR13JJvD3+CMIACMAcgecEKZov3CyBayYc3xBPf4c08onbN+5rBheLHObLhcUwTiNAj0oQWNWNw7Ss6jwJfzagjWyo10spddBfay/+LjqyqOZo52RTv+EKK98u1uFP5+BF+t3MWt8A9IvVhs4oP+mDQo0N+9rkDxH2MPSYZcG/ey+xEkso6vITGGyqhJXqIVF0crhBx944PLMEAwC9TbQlBkLRmdzRoZNkdOAoseRXm1qutliUqck2TTdAMQbz0neCcmj7nDcPoLbQJN2EssIi+9pIOSW3OEqisloEm2biwMH4isFA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(6029001)(4636009)(46966006)(36840700001)(54906003)(316002)(508600001)(186003)(1076003)(6916009)(44832011)(36860700001)(2616005)(36756003)(8676002)(2906002)(86362001)(70206006)(47076005)(6666004)(70586007)(5660300002)(83380400001)(336012)(4326008)(426003)(356005)(26005)(8936002)(81166007)(82310400003)(117716001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2021 01:10:09.3843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef0aa02f-b3db-4f09-27ad-08d9682e3fbd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1133 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Nicholas Kazlauskas [Why] This is a global parameter, not a per pipe parameter and it's useful for experimenting with the prefetch schedule to be adjustable from the SOC bb. [How] Add a parameter to the SOC bb, default is the existing policy for all DCN. Fill it in when filling SOC bb parameters. Revert the policy to use MinDCFClk at the same time since that's not going to give us P-State in most cases on the spreadsheet. Signed-off-by: Nicholas Kazlauskas Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 7 +++++-- drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index d090cb916767..2feffe75ca62 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -92,7 +92,7 @@ #define DC_LOGGER_INIT(logger) struct _vcs_dpi_ip_params_st dcn3_0_ip = { - .use_min_dcfclk = 1, + .use_min_dcfclk = 0, .clamp_min_dcfclk = 0, .odm_capable = 1, .gpuvm_enable = 0, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index e1a961a62add..e3d9f1decdfc 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -3644,8 +3644,7 @@ static double TruncToValidBPP( void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { struct vba_vars_st *v = &mode_lib->vba; - int MinPrefetchMode = 0; - int MaxPrefetchMode = 2; + int MinPrefetchMode, MaxPrefetchMode; int i; unsigned int j, k, m; bool EnoughWritebackUnits = true; @@ -3657,6 +3656,10 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l /*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/ + CalculateMinAndMaxPrefetchMode( + mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, + &MinPrefetchMode, &MaxPrefetchMode); + /*Scale Ratio, taps Support Check*/ v->ScaleRatioAndTapsSupport = true; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index 73f5be26abc4..0fad15020c74 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -244,6 +244,8 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib) mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support || mode_lib->vba.DummyPStateCheck; mode_lib->vba.AllowDramClockChangeOneDisplayVactive = soc->allow_dram_clock_one_display_vactive; + mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank = + soc->allow_dram_self_refresh_or_dram_clock_change_in_vblank; mode_lib->vba.Downspreading = soc->downspread_percent; mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new! @@ -733,8 +735,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.OverrideHostVMPageTableLevels; } - mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank = dm_try_to_allow_self_refresh_and_mclk_switch; - if (mode_lib->vba.OverrideGPUVMPageTableLevels) mode_lib->vba.GPUVMMaxPageTableLevels = mode_lib->vba.OverrideGPUVMPageTableLevels; -- 2.30.2