From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A9E8C432BE for ; Thu, 26 Aug 2021 15:20:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 623BB60F21 for ; Thu, 26 Aug 2021 15:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242956AbhHZPVm (ORCPT ); Thu, 26 Aug 2021 11:21:42 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56490 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242904AbhHZPVj (ORCPT ); Thu, 26 Aug 2021 11:21:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1629991250; x=1632583250; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=LfHR+esUZqjukvcNKRaf39fw5s9wBCQeVlt2BZrLEOk=; b=t7fforA6zG/rrswdR4SY8onuqW6nrhnulxA8Uk+qTGZDqRqQ/y7UO0BTR62nqTyM IU7c2iHRLMZ62dOsCUD7s7ig8+wXYwcnmnLODf/T+jJN1i4OqufyAKaSAhLhIx2X FHJpBHsd3SOz2wBYAubd3S1MWeyIX3IvpKwISQvfOzk=; X-AuditID: c39127d2-777be70000001c5c-17-6127b1529c5c Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id EF.C0.07260.251B7216; Thu, 26 Aug 2021 17:20:50 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021082617204983-1475685 ; Thu, 26 Aug 2021 17:20:49 +0200 From: Stefan Riedmueller To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer Cc: Stefan Riedmueller , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register Date: Thu, 26 Aug 2021 17:20:48 +0200 Message-Id: <20210826152049.4175381-1-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.08.2021 17:20:50, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.08.2021 17:20:50 X-TNEFEvaluated: 1 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsWyRoCBSzdoo3qiQd8SPotll44yWjy86m+x aupOFotNj6+xWnzsucdq0fVrJbPF5V1z2CwunnK1+Lt9E4vFv2sbWSxebBF34PZ4f6OV3WPn rLvsHptWdbJ5bF5S77Hx3Q4mj/6/Bh6fN8kFsEdx2aSk5mSWpRbp2yVwZSx9uJy94JhYRU9b B3MD40PhLkZODgkBE4mOPX+Zuhi5OIQEtjFKdO+8zA7hXGCUaOpazQZSxSZgJLFgWiNYlYjA dkaJF933GUESzAIdTBLzZriB2MICARLb961lAbFZBFQlPt3dyQRi8wrYSXQ9P8IIsU5eYual 7+wQcUGJkzOfsIAMlRC4wijR3/CLBaJISOL04rPMEAu0JZYtfM08gZFvFpKeWUhSCxiZVjEK 5WYmZ6cWZWbrFWRUlqQm66WkbmIEhvPhieqXdjD2zfE4xMjEwXiIUYKDWUmEd8F3tUQh3pTE yqrUovz4otKc1OJDjNIcLErivPd7mBKFBNITS1KzU1MLUotgskwcnFINjOoCYTrNe5Or3quv u8K273U3l/ehbt1D6sdbtINXGVZOFDHc3iIUeu+nx292M5nA2Vu4eG2fGcokGZ7elFTv1lt+ tf3Avmrlpi/ThAseFJ1pylTIPKQlU3qI/bmlzoo9rfIv2S9nJv++97bpeOz7v+KKZ3ZyWWqk pPMLzP928sSHF+84zvSaK7EUZyQaajEXFScCAOjCzutVAgAA Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The csi=5Fsel mux register is located in the CCM register base and not the CCM=5FANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM=5FANALOG=5FPLL=5FSYS=5FTOG register being fal= sely modified. Also remove the SET=5FRATE=5FPARENT flag since one possible supply for the csi=5Fsel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller --- drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 5dbb6a937732..206e4c43f68f 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -161,7 +161,6 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct de= vice=5Fnode *ccm=5Fnode) hws[IMX6UL=5FPLL5=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll5=5Fbypa= ss", base + 0xa0, 16, 1, pll5=5Fbypass=5Fsels, ARRAY=5FSIZE(pll5=5Fbypass= =5Fsels), CLK=5FSET=5FRATE=5FPARENT); hws[IMX6UL=5FPLL6=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll6=5Fbypa= ss", base + 0xe0, 16, 1, pll6=5Fbypass=5Fsels, ARRAY=5FSIZE(pll6=5Fbypass= =5Fsels), CLK=5FSET=5FRATE=5FPARENT); hws[IMX6UL=5FPLL7=5FBYPASS] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("pll7=5Fbypa= ss", base + 0x20, 16, 1, pll7=5Fbypass=5Fsels, ARRAY=5FSIZE(pll7=5Fbypass= =5Fsels), CLK=5FSET=5FRATE=5FPARENT); - hws[IMX6UL=5FCLK=5FCSI=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags("csi=5Fsel= ", base + 0x3c, 9, 2, csi=5Fsels, ARRAY=5FSIZE(csi=5Fsels), CLK=5FSET=5FRAT= E=5FPARENT); =20 /* Do not bypass PLLs initially */ clk=5Fset=5Fparent(hws[IMX6UL=5FPLL1=5FBYPASS]->clk, hws[IMX6UL=5FCLK=5FP= LL1]->clk); @@ -270,6 +269,7 @@ static void =5F=5Finit imx6ul=5Fclocks=5Finit(struct de= vice=5Fnode *ccm=5Fnode) hws[IMX6UL=5FCLK=5FECSPI=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux("ecspi=5Fsel",= base + 0x38, 18, 1, ecspi=5Fsels, ARRAY=5FSIZE(ecspi=5Fsels)); hws[IMX6UL=5FCLK=5FLCDIF=5FPRE=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux=5Fflags(= "lcdif=5Fpre=5Fsel", base + 0x38, 15, 3, lcdif=5Fpre=5Fsels, ARRAY=5FSIZE(l= cdif=5Fpre=5Fsels), CLK=5FSET=5FRATE=5FPARENT); hws[IMX6UL=5FCLK=5FLCDIF=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux("lcdif=5Fsel",= base + 0x38, 9, 3, lcdif=5Fsels, ARRAY=5FSIZE(lcdif=5Fsels)); + hws[IMX6UL=5FCLK=5FCSI=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux("csi=5Fsel", ba= se + 0x3c, 9, 2, csi=5Fsels, ARRAY=5FSIZE(csi=5Fsels)); =20 hws[IMX6UL=5FCLK=5FLDB=5FDI0=5FDIV=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux("ldb= =5Fdi0", base + 0x20, 10, 1, ldb=5Fdi0=5Fdiv=5Fsels, ARRAY=5FSIZE(ldb=5Fdi0= =5Fdiv=5Fsels)); hws[IMX6UL=5FCLK=5FLDB=5FDI1=5FDIV=5FSEL] =3D imx=5Fclk=5Fhw=5Fmux("ldb= =5Fdi1", base + 0x20, 11, 1, ldb=5Fdi1=5Fdiv=5Fsels, ARRAY=5FSIZE(ldb=5Fdi1= =5Fdiv=5Fsels)); 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Thu, 26 Aug 2021 17:20:50 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021082617204983-1475685 ; Thu, 26 Aug 2021 17:20:49 +0200 From: Stefan Riedmueller To: Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer Cc: Stefan Riedmueller , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] clk: imx: imx6ul: Move csi_sel mux to correct base register Date: Thu, 26 Aug 2021 17:20:48 +0200 Message-Id: <20210826152049.4175381-1-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.08.2021 17:20:50, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.08.2021 17:20:50 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsWyRoCBSzdoo3qiQd8SPotll44yWjy86m+x aupOFotNj6+xWnzsucdq0fVrJbPF5V1z2CwunnK1+Lt9E4vFv2sbWSxebBF34PZ4f6OV3WPn rLvsHptWdbJ5bF5S77Hx3Q4mj/6/Bh6fN8kFsEdx2aSk5mSWpRbp2yVwZSx9uJy94JhYRU9b B3MD40PhLkZODgkBE4mOPX+Zuhi5OIQEtjFKdO+8zA7hXGCUaOpazQZSxSZgJLFgWiNYlYjA dkaJF933GUESzAIdTBLzZriB2MICARLb961lAbFZBFQlPt3dyQRi8wrYSXQ9P8IIsU5eYual 7+wQcUGJkzOfsIAMlRC4wijR3/CLBaJISOL04rPMEAu0JZYtfM08gZFvFpKeWUhSCxiZVjEK 5WYmZ6cWZWbrFWRUlqQm66WkbmIEhvPhieqXdjD2zfE4xMjEwXiIUYKDWUmEd8F3tUQh3pTE yqrUovz4otKc1OJDjNIcLErivPd7mBKFBNITS1KzU1MLUotgskwcnFINjOoCYTrNe5Or3quv u8K273U3l/ehbt1D6sdbtINXGVZOFDHc3iIUeu+nx292M5nA2Vu4eG2fGcokGZ7elFTv1lt+ tf3Avmrlpi/ThAseFJ1pylTIPKQlU3qI/bmlzoo9rfIv2S9nJv++97bpeOz7v+KKZ3ZyWWqk pPMLzP928sSHF+84zvSaK7EUZyQaajEXFScCAOjCzutVAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210826_082100_422847_DD6AC348 X-CRM114-Status: GOOD ( 14.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller --- drivers/clk/imx/clk-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 5dbb6a937732..206e4c43f68f 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -161,7 +161,6 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); /* Do not bypass PLLs initially */ clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); @@ -270,6 +269,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) hws[IMX6UL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); hws[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_hw_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT); hws[IMX6UL_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); + hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); hws[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); hws[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel