From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9101BC4320A for ; Mon, 30 Aug 2021 12:21:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 76C6961155 for ; Mon, 30 Aug 2021 12:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237329AbhH3MUp (ORCPT ); Mon, 30 Aug 2021 08:20:45 -0400 Received: from mail.kernel.org ([198.145.29.99]:51556 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237375AbhH3MTj (ORCPT ); Mon, 30 Aug 2021 08:19:39 -0400 Received: from jic23-huawei (cpc108967-cmbg20-2-0-cust86.5-4.cable.virginm.net [81.101.6.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D77EB610FB; Mon, 30 Aug 2021 12:18:42 +0000 (UTC) Date: Mon, 30 Aug 2021 13:21:53 +0100 From: Jonathan Cameron To: Eugen Hristev Cc: , , , , , , Subject: Re: [PATCH v2 04/10] iio: adc: at91-sama5d2_adc: convert to platform specific data structures Message-ID: <20210830132153.78f8dac5@jic23-huawei> In-Reply-To: <20210824115441.681253-5-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> <20210824115441.681253-5-eugen.hristev@microchip.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 24 Aug 2021 14:54:35 +0300 Eugen Hristev wrote: > Convert the driver to platform specific structures. This means: > - create a register layout struct that will hold offsets for registers > - create a platform struct that will hold platform information (number of > channels, indexes for different channels and pointer to layout struct) > - convert specific macros that are platform dependent into platform variables > > This step is in fact a no-op, but allows the driver to be more flexible > and for future enhancement including adding new platforms that are partly > compatible with the current driver and differ slightly in register layout > or capabilities for example. > > Signed-off-by: Eugen Hristev > --- > drivers/iio/adc/at91-sama5d2_adc.c | 410 +++++++++++++++++------------ > 1 file changed, 247 insertions(+), 163 deletions(-) > > diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c > index 9d71dcffcf93..8ede18b8d789 100644 > --- a/drivers/iio/adc/at91-sama5d2_adc.c > +++ b/drivers/iio/adc/at91-sama5d2_adc.c > @@ -27,8 +27,9 @@ > #include > #include > > +struct at91_adc_reg_layout { > /* Control Register */ > -#define AT91_SAMA5D2_CR 0x00 > + u16 CR; > /* Software Reset */ > #define AT91_SAMA5D2_CR_SWRST BIT(0) > /* Start Conversion */ > @@ -39,7 +40,7 @@ > #define AT91_SAMA5D2_CR_CMPRST BIT(4) > > /* Mode Register */ > -#define AT91_SAMA5D2_MR 0x04 > + u16 MR; > /* Trigger Selection */ > #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) > /* ADTRG */ > @@ -82,19 +83,19 @@ > #define AT91_SAMA5D2_MR_USEQ BIT(31) > > /* Channel Sequence Register 1 */ > -#define AT91_SAMA5D2_SEQR1 0x08 > + u16 SEQR1; > /* Channel Sequence Register 2 */ > -#define AT91_SAMA5D2_SEQR2 0x0c > + u16 SEQR2; > /* Channel Enable Register */ > -#define AT91_SAMA5D2_CHER 0x10 > + u16 CHER; > /* Channel Disable Register */ > -#define AT91_SAMA5D2_CHDR 0x14 > + u16 CHDR; > /* Channel Status Register */ > -#define AT91_SAMA5D2_CHSR 0x18 > + u16 CHSR; > /* Last Converted Data Register */ > -#define AT91_SAMA5D2_LCDR 0x20 > + u16 LCDR; > /* Interrupt Enable Register */ > -#define AT91_SAMA5D2_IER 0x24 > + u16 IER; > /* Interrupt Enable Register - TS X measurement ready */ > #define AT91_SAMA5D2_IER_XRDY BIT(20) > /* Interrupt Enable Register - TS Y measurement ready */ > @@ -109,22 +110,23 @@ > #define AT91_SAMA5D2_IER_PEN BIT(29) > /* Interrupt Enable Register - No pen detect */ > #define AT91_SAMA5D2_IER_NOPEN BIT(30) > + > /* Interrupt Disable Register */ > -#define AT91_SAMA5D2_IDR 0x28 > + u16 IDR; > /* Interrupt Mask Register */ > -#define AT91_SAMA5D2_IMR 0x2c > + u16 IMR; > /* Interrupt Status Register */ > -#define AT91_SAMA5D2_ISR 0x30 > + u16 ISR; > /* Interrupt Status Register - Pen touching sense status */ > #define AT91_SAMA5D2_ISR_PENS BIT(31) > /* Last Channel Trigger Mode Register */ > -#define AT91_SAMA5D2_LCTMR 0x34 > + u16 LCTMR; > /* Last Channel Compare Window Register */ > -#define AT91_SAMA5D2_LCCWR 0x38 > + u16 LCCWR; > /* Overrun Status Register */ > -#define AT91_SAMA5D2_OVER 0x3c > + u16 OVER; > /* Extended Mode Register */ > -#define AT91_SAMA5D2_EMR 0x40 > + u16 EMR; > /* Extended Mode Register - Oversampling rate */ > #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) > #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) > @@ -134,22 +136,22 @@ > > /* Extended Mode Register - Averaging on single trigger event */ > #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) > + > /* Compare Window Register */ > -#define AT91_SAMA5D2_CWR 0x44 > + u16 CWR; > /* Channel Gain Register */ > -#define AT91_SAMA5D2_CGR 0x48 > - > + u16 CGR; > /* Channel Offset Register */ > -#define AT91_SAMA5D2_COR 0x4c > + u16 COR; > #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 > > /* Analog Control Register */ > -#define AT91_SAMA5D2_ACR 0x94 > + u16 ACR; > /* Analog Control Register - Pen detect sensitivity mask */ > #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) > > /* Touchscreen Mode Register */ > -#define AT91_SAMA5D2_TSMR 0xb0 > + u16 TSMR; > /* Touchscreen Mode Register - No touch mode */ > #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 > /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ > @@ -178,13 +180,13 @@ > #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) > > /* Touchscreen X Position Register */ > -#define AT91_SAMA5D2_XPOSR 0xb4 > + u16 XPOSR; > /* Touchscreen Y Position Register */ > -#define AT91_SAMA5D2_YPOSR 0xb8 > + u16 YPOSR; > /* Touchscreen Pressure Register */ > -#define AT91_SAMA5D2_PRESSR 0xbc > + u16 PRESSR; > /* Trigger Register */ > -#define AT91_SAMA5D2_TRGR 0xc0 > + u16 TRGR; > /* Mask for TRGMOD field of TRGR register */ > #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) > /* No trigger, only software trigger can start conversions */ > @@ -203,30 +205,52 @@ > #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) > > /* Correction Select Register */ > -#define AT91_SAMA5D2_COSR 0xd0 > + u16 COSR; > /* Correction Value Register */ > -#define AT91_SAMA5D2_CVR 0xd4 > + u16 CVR; > /* Channel Error Correction Register */ > -#define AT91_SAMA5D2_CECR 0xd8 > + u16 CECR; > /* Write Protection Mode Register */ > -#define AT91_SAMA5D2_WPMR 0xe4 > + u16 WPMR; > /* Write Protection Status Register */ > -#define AT91_SAMA5D2_WPSR 0xe8 > + u16 WPSR; > /* Version Register */ > -#define AT91_SAMA5D2_VERSION 0xfc > - > -#define AT91_SAMA5D2_HW_TRIG_CNT 3 > -#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 > -#define AT91_SAMA5D2_DIFF_CHAN_CNT 6 > - > -#define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT + 1) > + u16 VERSION; > +}; > > -#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT * 2) > -#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) > -#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) > -#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX > +static const struct at91_adc_reg_layout sama5d2_layout = { > + .CR = 0x00, > + .MR = 0x04, > + .SEQR1 = 0x08, > + .SEQR2 = 0x0c, > + .CHER = 0x10, > + .CHDR = 0x14, > + .CHSR = 0x18, > + .LCDR = 0x20, > + .IER = 0x24, > + .IDR = 0x28, > + .IMR = 0x2c, > + .ISR = 0x30, > + .LCTMR = 0x34, > + .LCCWR = 0x38, > + .OVER = 0x3c, > + .EMR = 0x40, > + .CWR = 0x44, > + .CGR = 0x48, > + .COR = 0x4c, > + .ACR = 0x94, > + .TSMR = 0xb0, > + .XPOSR = 0xb4, > + .YPOSR = 0xb8, > + .PRESSR = 0xbc, > + .TRGR = 0xc0, > + .COSR = 0xd0, > + .CVR = 0xd4, > + .CECR = 0xd8, > + .WPMR = 0xe4, > + .WPSR = 0xe8, > + .VERSION = 0xfc, > +}; > > #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ > #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 > @@ -235,18 +259,6 @@ > > #define AT91_SAMA5D2_MAX_POS_BITS 12 > > -/* > - * Maximum number of bytes to hold conversion from all channels > - * without the timestamp. > - */ > -#define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) > - > -/* This total must also include the timestamp */ > -#define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) > - > -#define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) > - > #define AT91_HWFIFO_MAX_SIZE_STR "128" > #define AT91_HWFIFO_MAX_SIZE 128 > > @@ -255,12 +267,12 @@ > #define AT91_OSR_4SAMPLES 4 > #define AT91_OSR_16SAMPLES 16 > > -#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ > +#define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ > { \ > .type = IIO_VOLTAGE, \ > .channel = num, \ > .address = addr, \ > - .scan_index = num, \ > + .scan_index = index, \ > .scan_type = { \ > .sign = 'u', \ > .realbits = 14, \ > @@ -274,14 +286,14 @@ > .indexed = 1, \ > } > > -#define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ > +#define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \ > { \ > .type = IIO_VOLTAGE, \ > .differential = 1, \ > .channel = num, \ > .channel2 = num2, \ > .address = addr, \ > - .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ > + .scan_index = index, \ > .scan_type = { \ > .sign = 's', \ > .realbits = 14, \ > @@ -328,13 +340,48 @@ > .datasheet_name = name, \ > } > > -#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) > -#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) > +#define at91_adc_readl(st, reg) \ > + readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) I was a bit in two minds about whether this should be in capitals to make it clear macro magic is going on, or whether lowercase is fine. In the end I couldn't make up my mind so will accept it like this! :) Jonathan From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4FDFC432BE for ; Mon, 30 Aug 2021 12:20:31 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1AD0610FB for ; Mon, 30 Aug 2021 12:20:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A1AD0610FB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=22ZWO2EIJG42uZZZbfhn3xtBiC4uRyus8qLfuhGnO5g=; b=e5OqY9SjWQ3xMm p2dl6N+fOPHKiG91mLFawxZVxeSeAAbsS/gNqPtRtKRMSYAWEEm8OsZQtNU3moc6/8vT7yPcNys2n eggpLEp+FPP2PaorXp8xVoc1pG110iJnhYe3k5kFgAr37GJNFrK/kZTrPHOZNs4s90Nbh+kUhBBwq SM22rrdeUR9mKDQyB8YLOFi7zVn/dJeLVvXm3kKU0kPFdRVz0DraZPGzMtz+lA9kZRfjOhqqB/C4r 9hawMR49ILkXRfUaQlRPuQfTtEA6LQPBHnDPkEKSC3BFihljfuJqf2vHWpmr1U1sTJE1aAZZ7T0jb 8QZpClWqEPCxLnOjDVcA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKgFW-00HDQP-0N; Mon, 30 Aug 2021 12:18:50 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKgFS-00HDQ0-12 for linux-arm-kernel@lists.infradead.org; Mon, 30 Aug 2021 12:18:47 +0000 Received: from jic23-huawei (cpc108967-cmbg20-2-0-cust86.5-4.cable.virginm.net [81.101.6.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D77EB610FB; Mon, 30 Aug 2021 12:18:42 +0000 (UTC) Date: Mon, 30 Aug 2021 13:21:53 +0100 From: Jonathan Cameron To: Eugen Hristev Subject: Re: [PATCH v2 04/10] iio: adc: at91-sama5d2_adc: convert to platform specific data structures Message-ID: <20210830132153.78f8dac5@jic23-huawei> In-Reply-To: <20210824115441.681253-5-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> <20210824115441.681253-5-eugen.hristev@microchip.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210830_051846_165793_0F9AC0B4 X-CRM114-Status: GOOD ( 29.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, ludovic.desroches@microchip.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 24 Aug 2021 14:54:35 +0300 Eugen Hristev wrote: > Convert the driver to platform specific structures. This means: > - create a register layout struct that will hold offsets for registers > - create a platform struct that will hold platform information (number of > channels, indexes for different channels and pointer to layout struct) > - convert specific macros that are platform dependent into platform variables > > This step is in fact a no-op, but allows the driver to be more flexible > and for future enhancement including adding new platforms that are partly > compatible with the current driver and differ slightly in register layout > or capabilities for example. > > Signed-off-by: Eugen Hristev > --- > drivers/iio/adc/at91-sama5d2_adc.c | 410 +++++++++++++++++------------ > 1 file changed, 247 insertions(+), 163 deletions(-) > > diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c > index 9d71dcffcf93..8ede18b8d789 100644 > --- a/drivers/iio/adc/at91-sama5d2_adc.c > +++ b/drivers/iio/adc/at91-sama5d2_adc.c > @@ -27,8 +27,9 @@ > #include > #include > > +struct at91_adc_reg_layout { > /* Control Register */ > -#define AT91_SAMA5D2_CR 0x00 > + u16 CR; > /* Software Reset */ > #define AT91_SAMA5D2_CR_SWRST BIT(0) > /* Start Conversion */ > @@ -39,7 +40,7 @@ > #define AT91_SAMA5D2_CR_CMPRST BIT(4) > > /* Mode Register */ > -#define AT91_SAMA5D2_MR 0x04 > + u16 MR; > /* Trigger Selection */ > #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) > /* ADTRG */ > @@ -82,19 +83,19 @@ > #define AT91_SAMA5D2_MR_USEQ BIT(31) > > /* Channel Sequence Register 1 */ > -#define AT91_SAMA5D2_SEQR1 0x08 > + u16 SEQR1; > /* Channel Sequence Register 2 */ > -#define AT91_SAMA5D2_SEQR2 0x0c > + u16 SEQR2; > /* Channel Enable Register */ > -#define AT91_SAMA5D2_CHER 0x10 > + u16 CHER; > /* Channel Disable Register */ > -#define AT91_SAMA5D2_CHDR 0x14 > + u16 CHDR; > /* Channel Status Register */ > -#define AT91_SAMA5D2_CHSR 0x18 > + u16 CHSR; > /* Last Converted Data Register */ > -#define AT91_SAMA5D2_LCDR 0x20 > + u16 LCDR; > /* Interrupt Enable Register */ > -#define AT91_SAMA5D2_IER 0x24 > + u16 IER; > /* Interrupt Enable Register - TS X measurement ready */ > #define AT91_SAMA5D2_IER_XRDY BIT(20) > /* Interrupt Enable Register - TS Y measurement ready */ > @@ -109,22 +110,23 @@ > #define AT91_SAMA5D2_IER_PEN BIT(29) > /* Interrupt Enable Register - No pen detect */ > #define AT91_SAMA5D2_IER_NOPEN BIT(30) > + > /* Interrupt Disable Register */ > -#define AT91_SAMA5D2_IDR 0x28 > + u16 IDR; > /* Interrupt Mask Register */ > -#define AT91_SAMA5D2_IMR 0x2c > + u16 IMR; > /* Interrupt Status Register */ > -#define AT91_SAMA5D2_ISR 0x30 > + u16 ISR; > /* Interrupt Status Register - Pen touching sense status */ > #define AT91_SAMA5D2_ISR_PENS BIT(31) > /* Last Channel Trigger Mode Register */ > -#define AT91_SAMA5D2_LCTMR 0x34 > + u16 LCTMR; > /* Last Channel Compare Window Register */ > -#define AT91_SAMA5D2_LCCWR 0x38 > + u16 LCCWR; > /* Overrun Status Register */ > -#define AT91_SAMA5D2_OVER 0x3c > + u16 OVER; > /* Extended Mode Register */ > -#define AT91_SAMA5D2_EMR 0x40 > + u16 EMR; > /* Extended Mode Register - Oversampling rate */ > #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) > #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) > @@ -134,22 +136,22 @@ > > /* Extended Mode Register - Averaging on single trigger event */ > #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) > + > /* Compare Window Register */ > -#define AT91_SAMA5D2_CWR 0x44 > + u16 CWR; > /* Channel Gain Register */ > -#define AT91_SAMA5D2_CGR 0x48 > - > + u16 CGR; > /* Channel Offset Register */ > -#define AT91_SAMA5D2_COR 0x4c > + u16 COR; > #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 > > /* Analog Control Register */ > -#define AT91_SAMA5D2_ACR 0x94 > + u16 ACR; > /* Analog Control Register - Pen detect sensitivity mask */ > #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) > > /* Touchscreen Mode Register */ > -#define AT91_SAMA5D2_TSMR 0xb0 > + u16 TSMR; > /* Touchscreen Mode Register - No touch mode */ > #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 > /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ > @@ -178,13 +180,13 @@ > #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) > > /* Touchscreen X Position Register */ > -#define AT91_SAMA5D2_XPOSR 0xb4 > + u16 XPOSR; > /* Touchscreen Y Position Register */ > -#define AT91_SAMA5D2_YPOSR 0xb8 > + u16 YPOSR; > /* Touchscreen Pressure Register */ > -#define AT91_SAMA5D2_PRESSR 0xbc > + u16 PRESSR; > /* Trigger Register */ > -#define AT91_SAMA5D2_TRGR 0xc0 > + u16 TRGR; > /* Mask for TRGMOD field of TRGR register */ > #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) > /* No trigger, only software trigger can start conversions */ > @@ -203,30 +205,52 @@ > #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) > > /* Correction Select Register */ > -#define AT91_SAMA5D2_COSR 0xd0 > + u16 COSR; > /* Correction Value Register */ > -#define AT91_SAMA5D2_CVR 0xd4 > + u16 CVR; > /* Channel Error Correction Register */ > -#define AT91_SAMA5D2_CECR 0xd8 > + u16 CECR; > /* Write Protection Mode Register */ > -#define AT91_SAMA5D2_WPMR 0xe4 > + u16 WPMR; > /* Write Protection Status Register */ > -#define AT91_SAMA5D2_WPSR 0xe8 > + u16 WPSR; > /* Version Register */ > -#define AT91_SAMA5D2_VERSION 0xfc > - > -#define AT91_SAMA5D2_HW_TRIG_CNT 3 > -#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 > -#define AT91_SAMA5D2_DIFF_CHAN_CNT 6 > - > -#define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT + 1) > + u16 VERSION; > +}; > > -#define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT * 2) > -#define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) > -#define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) > -#define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX > +static const struct at91_adc_reg_layout sama5d2_layout = { > + .CR = 0x00, > + .MR = 0x04, > + .SEQR1 = 0x08, > + .SEQR2 = 0x0c, > + .CHER = 0x10, > + .CHDR = 0x14, > + .CHSR = 0x18, > + .LCDR = 0x20, > + .IER = 0x24, > + .IDR = 0x28, > + .IMR = 0x2c, > + .ISR = 0x30, > + .LCTMR = 0x34, > + .LCCWR = 0x38, > + .OVER = 0x3c, > + .EMR = 0x40, > + .CWR = 0x44, > + .CGR = 0x48, > + .COR = 0x4c, > + .ACR = 0x94, > + .TSMR = 0xb0, > + .XPOSR = 0xb4, > + .YPOSR = 0xb8, > + .PRESSR = 0xbc, > + .TRGR = 0xc0, > + .COSR = 0xd0, > + .CVR = 0xd4, > + .CECR = 0xd8, > + .WPMR = 0xe4, > + .WPSR = 0xe8, > + .VERSION = 0xfc, > +}; > > #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ > #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 > @@ -235,18 +259,6 @@ > > #define AT91_SAMA5D2_MAX_POS_BITS 12 > > -/* > - * Maximum number of bytes to hold conversion from all channels > - * without the timestamp. > - */ > -#define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ > - AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) > - > -/* This total must also include the timestamp */ > -#define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) > - > -#define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) > - > #define AT91_HWFIFO_MAX_SIZE_STR "128" > #define AT91_HWFIFO_MAX_SIZE 128 > > @@ -255,12 +267,12 @@ > #define AT91_OSR_4SAMPLES 4 > #define AT91_OSR_16SAMPLES 16 > > -#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ > +#define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr) \ > { \ > .type = IIO_VOLTAGE, \ > .channel = num, \ > .address = addr, \ > - .scan_index = num, \ > + .scan_index = index, \ > .scan_type = { \ > .sign = 'u', \ > .realbits = 14, \ > @@ -274,14 +286,14 @@ > .indexed = 1, \ > } > > -#define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ > +#define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr) \ > { \ > .type = IIO_VOLTAGE, \ > .differential = 1, \ > .channel = num, \ > .channel2 = num2, \ > .address = addr, \ > - .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ > + .scan_index = index, \ > .scan_type = { \ > .sign = 's', \ > .realbits = 14, \ > @@ -328,13 +340,48 @@ > .datasheet_name = name, \ > } > > -#define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) > -#define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) > +#define at91_adc_readl(st, reg) \ > + readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg) I was a bit in two minds about whether this should be in capitals to make it clear macro magic is going on, or whether lowercase is fine. In the end I couldn't make up my mind so will accept it like this! :) Jonathan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel