From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 424ADC432BE for ; Tue, 31 Aug 2021 02:14:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25C036103D for ; Tue, 31 Aug 2021 02:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239424AbhHaCPa (ORCPT ); Mon, 30 Aug 2021 22:15:30 -0400 Received: from mo-csw1516.securemx.jp ([210.130.202.155]:58600 "EHLO mo-csw.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239376AbhHaCP2 (ORCPT ); Mon, 30 Aug 2021 22:15:28 -0400 Received: by mo-csw.securemx.jp (mx-mo-csw1516) id 17V2EUa2022033; Tue, 31 Aug 2021 11:14:30 +0900 X-Iguazu-Qid: 34trdvrI75kL3fQ1Yi X-Iguazu-QSIG: v=2; s=0; t=1630376070; q=34trdvrI75kL3fQ1Yi; m=enqtohIq2eRDuL61o6eYoKfPFuSw91zMK8OV2c3zi3A= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1510) id 17V2EUbk016230 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 31 Aug 2021 11:14:30 +0900 Received: from enc01.toshiba.co.jp (enc01.toshiba.co.jp [106.186.93.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by imx2-a.toshiba.co.jp (Postfix) with ESMTPS id 1866310009F; Tue, 31 Aug 2021 11:14:30 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.toshiba.co.jp with ESMTP id 17V2ETgh024714; Tue, 31 Aug 2021 11:14:29 +0900 Date: Tue, 31 Aug 2021 11:14:28 +0900 From: Nobuhiro Iwamatsu To: Stephen Boyd Cc: Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/4] dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC X-TSB-HOP: ON Message-ID: <20210831021428.rsjzi6vtv2q3wnkb@toshiba.co.jp> References: <20210804092244.390376-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210804092244.390376-2-nobuhiro1.iwamatsu@toshiba.co.jp> <163021379431.2676726.15668763072935534900@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <163021379431.2676726.15668763072935534900@swboyd.mtv.corp.google.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Thanks for your review. On Sat, Aug 28, 2021 at 10:09:54PM -0700, Stephen Boyd wrote: > Quoting Nobuhiro Iwamatsu (2021-08-04 02:22:41) > > Add device tree bindings for PLL of Toshiba Visconti TMPV770x SoC series. > > > > Signed-off-by: Nobuhiro Iwamatsu > > --- > > .../clock/toshiba,tmpv770x-pipllct.yaml | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > new file mode 100644 > > index 000000000000..7b7300ce96d6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > @@ -0,0 +1,57 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings > > + > > +maintainers: > > + - Nobuhiro Iwamatsu > > + > > +description: > > + Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X. > > + > > +properties: > > + compatible: > > + const: toshiba,tmpv7708-pipllct > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > + clocks: > > + description: External reference clock (OSC2) > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - "#clock-cells" > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + > > + osc2_clk: osc2-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <20000000>; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pipllct: clock-controller@24220000 { > > + compatible = "toshiba,tmpv7708-pipllct"; > > The driver makes it look like this is actually part of a syscon node. Is > that right? It's not clear to me that this is a syscon. But then looking > at the binding it seems that one device has been split up into PLL and > "not PLL" parts sort of arbitrarily. This is the driver that controls the PIPLLCT device that produces the PLL. This device only has the ability to generate his PLL, no other features. I have received similar comments in the driver patch from you, so I will check that as well. > > > + reg = <0 0x24220000 0 0x820>; > > + #clock-cells = <1>; > > + clocks = <&osc2_clk>; > > + }; > > + }; > > +... > Best regards, Nobuhiro From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D836C432BE for ; Tue, 31 Aug 2021 02:16:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 160FF601FD for ; Tue, 31 Aug 2021 02:16:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 160FF601FD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=toshiba.co.jp Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GhwQObnchduwkfqfopXAu5BaZCbdXNcYHJr07wmhNwo=; b=3FFDuKa2RWdxVn 9OQjOfSxdpFYANgU5quuWmfDDtkA7zgD0qZVd1qMrxhHug32QUhLU+je/viRbnu61vcbi38wzd+7/ 2XekPWDao+l3uyL+cHT+wwFsDSQnWV/UEjaR4WgmH47hNZzBTtCudSl8zxEZ9B3uofU+3ubZhn7J0 K/Ou0Hzv6bME0/S6m8Y+E+D4Hm6Ak9kV3ZEEa7GEXM5yvKFmwe8MFO50h+Va+Ay+i+H1uiVTg94mW kbZBB29jv9Q8kY1vO3xFm0di9lGDd5V4Qp9HM7jmL/iPIskvP6ZA5C8Ue8NdEky370hmprlRQQc/I DJCrhsIW01TqdvhCW30g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKtIf-000zV5-2X; Tue, 31 Aug 2021 02:14:57 +0000 Received: from mo-csw1114.securemx.jp ([210.130.202.156] helo=mo-csw.securemx.jp) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mKtIY-000zT9-LV for linux-arm-kernel@lists.infradead.org; Tue, 31 Aug 2021 02:14:54 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1114) id 17V2EXZ0023480; Tue, 31 Aug 2021 11:14:34 +0900 X-Iguazu-Qid: 2wHHPNX9aLgw0u9hdg X-Iguazu-QSIG: v=2; s=0; t=1630376073; q=2wHHPNX9aLgw0u9hdg; m=4TQjfpJF1MCzACgiDuc0MnPSNhvQ+p0rrA/aMIFVfX4= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1110) id 17V2EUbO030283 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 31 Aug 2021 11:14:32 +0900 Received: from enc01.toshiba.co.jp (enc01.toshiba.co.jp [106.186.93.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by imx2-a.toshiba.co.jp (Postfix) with ESMTPS id 22AF61000A1; Tue, 31 Aug 2021 11:14:30 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.toshiba.co.jp with ESMTP id 17V2ETbD024713; Tue, 31 Aug 2021 11:14:29 +0900 Date: Tue, 31 Aug 2021 11:14:28 +0900 From: Nobuhiro Iwamatsu To: Stephen Boyd Cc: Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/4] dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC X-TSB-HOP: ON Message-ID: <20210831021428.rsjzi6vtv2q3wnkb@toshiba.co.jp> References: <20210804092244.390376-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210804092244.390376-2-nobuhiro1.iwamatsu@toshiba.co.jp> <163021379431.2676726.15668763072935534900@swboyd.mtv.corp.google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <163021379431.2676726.15668763072935534900@swboyd.mtv.corp.google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210830_191451_028893_8FFDEF9C X-CRM114-Status: GOOD ( 24.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Thanks for your review. On Sat, Aug 28, 2021 at 10:09:54PM -0700, Stephen Boyd wrote: > Quoting Nobuhiro Iwamatsu (2021-08-04 02:22:41) > > Add device tree bindings for PLL of Toshiba Visconti TMPV770x SoC series. > > > > Signed-off-by: Nobuhiro Iwamatsu > > --- > > .../clock/toshiba,tmpv770x-pipllct.yaml | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > new file mode 100644 > > index 000000000000..7b7300ce96d6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pipllct.yaml > > @@ -0,0 +1,57 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Toshiba Visconti5 TMPV770X PLL Controller Device Tree Bindings > > + > > +maintainers: > > + - Nobuhiro Iwamatsu > > + > > +description: > > + Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X. > > + > > +properties: > > + compatible: > > + const: toshiba,tmpv7708-pipllct > > + > > + reg: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + > > + clocks: > > + description: External reference clock (OSC2) > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - "#clock-cells" > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + > > + osc2_clk: osc2-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <20000000>; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pipllct: clock-controller@24220000 { > > + compatible = "toshiba,tmpv7708-pipllct"; > > The driver makes it look like this is actually part of a syscon node. Is > that right? It's not clear to me that this is a syscon. But then looking > at the binding it seems that one device has been split up into PLL and > "not PLL" parts sort of arbitrarily. This is the driver that controls the PIPLLCT device that produces the PLL. This device only has the ability to generate his PLL, no other features. I have received similar comments in the driver patch from you, so I will check that as well. > > > + reg = <0 0x24220000 0 0x820>; > > + #clock-cells = <1>; > > + clocks = <&osc2_clk>; > > + }; > > + }; > > +... > Best regards, Nobuhiro _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel