From: Zong Li <zong.li@sifive.com>
To: rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com,
seanga2@gmail.com, green.wan@sifive.com,
paul.walmsley@sifive.com, sjg@chromium.org, u-boot@lists.denx.de
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v4 4/4] riscv: lib: modify the indent
Date: Tue, 31 Aug 2021 17:20:38 +0800 [thread overview]
Message-ID: <20210831092038.21669-5-zong.li@sifive.com> (raw)
In-Reply-To: <20210831092038.21669-1-zong.li@sifive.com>
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index ec8fe201d3..874963d731 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -8,7 +8,7 @@
#define _ASM_RISCV_CACHE_H
/* cache */
-void cache_flush(void);
+void cache_flush(void);
/*
* The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
--
2.32.0
prev parent reply other threads:[~2021-08-31 9:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-31 9:20 [PATCH v4 0/4] Support SiFive Composable cache driver Zong Li
2021-08-31 9:20 ` [PATCH v4 1/4] cache: add sifive composable " Zong Li
[not found] ` <HK0PR03MB29948AB105A6AA7611CDBFE4C1CD9@HK0PR03MB2994.apcprd03.prod.outlook.com>
2021-09-01 1:54 ` Rick Chen
2021-08-31 9:20 ` [PATCH v4 2/4] riscv: lib: implement enable_caches for sifive cache Zong Li
[not found] ` <HK0PR03MB2994094F62B00CE3E12CFA59C1CD9@HK0PR03MB2994.apcprd03.prod.outlook.com>
2021-09-01 2:06 ` Rick Chen
2021-09-01 2:50 ` Zong Li
2021-08-31 9:20 ` [PATCH v4 3/4] board: sifive: use ccache driver instead of helper function Zong Li
2021-08-31 9:20 ` Zong Li [this message]
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