All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com,
	Richard Henderson <richard.henderson@linaro.org>,
	Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 28/33] target/riscv: Use {get,dest}_gpr for RVA
Date: Wed,  1 Sep 2021 12:09:53 +1000	[thread overview]
Message-ID: <20210901020958.458454-29-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210901020958.458454-1-alistair.francis@opensource.wdc.com>

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-20-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rva.c.inc | 47 ++++++++++---------------
 1 file changed, 19 insertions(+), 28 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 3cc3c3b073..6ea07d89b0 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -18,11 +18,10 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    /* Put addr in load_res, data in load_val.  */
-    gen_get_gpr(ctx, src1, a->rs1);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -30,33 +29,33 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
     if (a->aq) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
+
+    /* Put addr in load_res, data in load_val.  */
     tcg_gen_mov_tl(load_res, src1);
     gen_set_gpr(ctx, a->rd, load_val);
 
-    tcg_temp_free(src1);
     return true;
 }
 
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
+    TCGv dest, src1, src2;
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    gen_get_gpr(ctx, src1, a->rs1);
+    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
-    gen_get_gpr(ctx, src2, a->rs2);
     /*
      * Note that the TCG atomic primitives are SC,
      * so we can ignore AQ/RL along this path.
      */
-    tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+    dest = dest_gpr(ctx, a->rd);
+    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
                               ctx->mem_idx, mop);
-    tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
-    gen_set_gpr(ctx, a->rd, dat);
+    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
+    gen_set_gpr(ctx, a->rd, dest);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -65,8 +64,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      * provide the memory barrier implied by AQ/RL.
      */
     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
-    tcg_gen_movi_tl(dat, 1);
-    gen_set_gpr(ctx, a->rd, dat);
+    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
 
     gen_set_label(l2);
     /*
@@ -75,9 +73,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      */
     tcg_gen_movi_tl(load_res, -1);
 
-    tcg_temp_free(dat);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
     return true;
 }
 
@@ -85,17 +80,13 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
                     MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, src1, a->rs1);
-    gen_get_gpr(ctx, src2, a->rs2);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    (*func)(src2, src1, src2, ctx->mem_idx, mop);
+    func(dest, src1, src2, ctx->mem_idx, mop);
 
-    gen_set_gpr(ctx, a->rd, src2);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-- 
2.31.1



  parent reply	other threads:[~2021-09-01  2:28 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01  2:09 [PULL 00/33] riscv-to-apply queue Alistair Francis
2021-09-01  2:09 ` [PULL 01/33] hw/char: Add config for shakti uart Alistair Francis
2021-09-01  2:09 ` [PULL 02/33] hw/riscv: virt: Move flash node to root Alistair Francis
2021-09-01  2:09 ` [PULL 03/33] target/riscv: Correct a comment in riscv_csrrw() Alistair Francis
2021-09-01  2:09 ` [PULL 04/33] target/riscv: Don't wrongly override isa version Alistair Francis
2021-09-01  2:09 ` [PULL 05/33] target/riscv: Add User CSRs read-only check Alistair Francis
2021-09-01  2:09 ` [PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv() Alistair Francis
2021-09-01  2:09 ` [PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp() Alistair Francis
2021-09-01  2:09 ` [PULL 08/33] hw/core/register: Add more 64-bit utilities Alistair Francis
2021-09-01  2:09 ` [PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64 Alistair Francis
2021-09-01  2:09 ` [PULL 10/33] target/riscv: Use tcg_constant_* Alistair Francis
2021-09-01  2:09 ` [PULL 11/33] tests/tcg/riscv64: Add test for division Alistair Francis
2021-09-01  2:09 ` [PULL 12/33] target/riscv: Clean up division helpers Alistair Francis
2021-09-01  2:09 ` [PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Alistair Francis
2021-09-01  2:09 ` [PULL 14/33] target/riscv: Introduce DisasExtend and new helpers Alistair Francis
2021-09-01  2:09 ` [PULL 15/33] target/riscv: Add DisasExtend to gen_arith* Alistair Francis
2021-09-01  2:09 ` [PULL 16/33] target/riscv: Remove gen_arith_div* Alistair Francis
2021-09-01  2:09 ` [PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu Alistair Francis
2021-09-01  2:09 ` [PULL 18/33] target/riscv: Move gen_* helpers for RVM Alistair Francis
2021-09-01  2:09 ` [PULL 19/33] target/riscv: Move gen_* helpers for RVB Alistair Francis
2021-09-01  2:09 ` [PULL 20/33] target/riscv: Add DisasExtend to gen_unary Alistair Francis
2021-09-01  2:09 ` [PULL 21/33] target/riscv: Use DisasExtend in shift operations Alistair Francis
2021-09-01  2:09 ` [PULL 22/33] target/riscv: Use extracts for sraiw and srliw Alistair Francis
2021-09-01  2:09 ` [PULL 23/33] target/riscv: Use get_gpr in branches Alistair Francis
2021-09-01  2:09 ` [PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store Alistair Francis
2021-09-01  2:09 ` [PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation Alistair Francis
2021-09-01  2:09 ` [PULL 26/33] target/riscv: Fix hgeie, hgeip Alistair Francis
2021-09-01  2:09 ` [PULL 27/33] target/riscv: Reorg csr instructions Alistair Francis
2021-09-01  2:09 ` Alistair Francis [this message]
2021-09-01  2:09 ` [PULL 29/33] target/riscv: Use gen_shift_imm_fn for slli_uw Alistair Francis
2021-09-01  2:09 ` [PULL 30/33] target/riscv: Use {get,dest}_gpr for RVF Alistair Francis
2021-09-01  2:09 ` [PULL 31/33] target/riscv: Use {get,dest}_gpr for RVD Alistair Francis
2021-09-01  2:09 ` [PULL 32/33] target/riscv: Tidy trans_rvh.c.inc Alistair Francis
2021-09-01  2:09 ` [PULL 33/33] target/riscv: Use {get,dest}_gpr for RVV Alistair Francis
2021-09-01  9:56 ` [PULL 00/33] riscv-to-apply queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210901020958.458454-29-alistair.francis@opensource.wdc.com \
    --to=alistair.francis@opensource.wdc.com \
    --cc=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=bmeng.cn@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.