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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id g2sm7174467pfo.154.2021.08.31.20.27.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Aug 2021 20:27:45 -0700 (PDT) From: Bin Meng To: Damien Hedde , "Edgar E . Iglesias" , Alistair Francis , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/5] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() Date: Wed, 1 Sep 2021 11:27:24 +0800 Message-Id: <20210901032724.23256-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901032724.23256-1-bmeng.cn@gmail.com> References: <20210901032724.23256-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Read or write to uart registers when unclocked or in reset should be ignored. Add the check there, and as a result of this, the check in uart_write_tx_fifo() is now unnecessary. Signed-off-by: Bin Meng --- Changes in v2: - new patch: hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read,write}() hw/char/cadence_uart.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 8bcf2b718a..5f5a4645ac 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -335,11 +335,6 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond, static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, int size) { - /* ignore characters when unclocked or in reset */ - if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { - return; - } - if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) { return; } @@ -416,6 +411,11 @@ static MemTxResult uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s = opaque; + /* ignore access when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return MEMTX_ERROR; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { @@ -476,6 +476,11 @@ static MemTxResult uart_read(void *opaque, hwaddr offset, CadenceUARTState *s = opaque; uint32_t c = 0; + /* ignore access when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return MEMTX_ERROR; + } + offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { return MEMTX_DECODE_ERROR; -- 2.25.1