From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Pavan Nikhilesh <pbhagavatula@marvell.com>,
Shijith Thotton <sthotton@marvell.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>,
"Kiran Kumar K" <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH 17/27] net/cnxk: add cn9k Rx support for security offload
Date: Thu, 2 Sep 2021 07:44:55 +0530 [thread overview]
Message-ID: <20210902021505.17607-18-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com>
Add support to receive CPT processed packets on Rx.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
drivers/event/cnxk/cn9k_eventdev.c | 153 ++++----
drivers/event/cnxk/cn9k_worker.h | 7 +-
drivers/event/cnxk/cn9k_worker_deq.c | 2 +-
drivers/event/cnxk/cn9k_worker_deq_burst.c | 2 +-
drivers/event/cnxk/cn9k_worker_deq_ca.c | 2 +-
drivers/event/cnxk/cn9k_worker_deq_tmo.c | 2 +-
drivers/event/cnxk/cn9k_worker_dual_deq.c | 2 +-
drivers/event/cnxk/cn9k_worker_dual_deq_burst.c | 2 +-
drivers/event/cnxk/cn9k_worker_dual_deq_ca.c | 2 +-
drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c | 2 +-
drivers/net/cnxk/cn9k_rx.c | 31 +-
drivers/net/cnxk/cn9k_rx.h | 440 +++++++++++++++++++-----
drivers/net/cnxk/cn9k_rx_mseg.c | 2 +-
drivers/net/cnxk/cn9k_rx_vec.c | 2 +-
drivers/net/cnxk/cn9k_rx_vec_mseg.c | 2 +-
drivers/net/cnxk/cnxk_ethdev.h | 3 +
16 files changed, 461 insertions(+), 195 deletions(-)
diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c
index 6601c44..e91234e 100644
--- a/drivers/event/cnxk/cn9k_eventdev.c
+++ b/drivers/event/cnxk/cn9k_eventdev.c
@@ -10,7 +10,8 @@
#define CN9K_DUAL_WS_PAIR_ID(x, id) (((x)*CN9K_DUAL_WS_NB_WS) + id)
#define CN9K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
- deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
+ deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \
+ [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \
[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \
@@ -329,178 +330,184 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)
{
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
/* Single WS modes */
- const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
+ const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
+ const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
+ const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
+ const event_dequeue_burst_t
+ sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,
+ const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,
+ const event_dequeue_burst_t
+ sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
+ const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
+ const event_dequeue_burst_t
+ sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
+ const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
+ sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_tmo_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,
+ const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,
+ sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_deq_ca_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
/* Dual WS modes */
- const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
+ const event_dequeue_t sso_hws_dual_deq[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_burst_t sso_hws_dual_deq_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
+ const event_dequeue_burst_t
+ sso_hws_dual_deq_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
+ const event_dequeue_t sso_hws_dual_deq_tmo[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
+ sso_hws_dual_deq_tmo_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,
+ const event_dequeue_t sso_hws_dual_deq_ca[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_dual_deq_ca_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,
+ sso_hws_dual_deq_ca_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
+ const event_dequeue_t sso_hws_dual_deq_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_dual_deq_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
+ sso_hws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
+ const event_dequeue_t sso_hws_dual_deq_tmo_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
+ sso_hws_dual_deq_tmo_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = \
+ cn9k_sso_hws_dual_deq_tmo_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,
+ const event_dequeue_t sso_hws_dual_deq_ca_seg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
const event_dequeue_burst_t
- sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
+ sso_hws_dual_deq_ca_seg_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = \
+ cn9k_sso_hws_dual_deq_ca_seg_burst_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h
index 3e8f214..f1d2e47 100644
--- a/drivers/event/cnxk/cn9k_worker.h
+++ b/drivers/event/cnxk/cn9k_worker.h
@@ -5,6 +5,9 @@
#ifndef __CN9K_WORKER_H__
#define __CN9K_WORKER_H__
+#include <rte_eventdev.h>
+#include <rte_vect.h>
+
#include "cnxk_ethdev.h"
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
@@ -380,7 +383,7 @@ uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],
uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],
uint16_t nb_events);
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_deq_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks); \
uint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \
@@ -415,7 +418,7 @@ uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],
NIX_RX_FASTPATH_MODES
#undef R
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks); \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \
diff --git a/drivers/event/cnxk/cn9k_worker_deq.c b/drivers/event/cnxk/cn9k_worker_deq.c
index 51ccaf4..d65c72a 100644
--- a/drivers/event/cnxk/cn9k_worker_deq.c
+++ b/drivers/event/cnxk/cn9k_worker_deq.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_deq_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/event/cnxk/cn9k_worker_deq_burst.c b/drivers/event/cnxk/cn9k_worker_deq_burst.c
index 4e28014..42dc59b 100644
--- a/drivers/event/cnxk/cn9k_worker_deq_burst.c
+++ b/drivers/event/cnxk/cn9k_worker_deq_burst.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_deq_burst_##name( \
void *port, struct rte_event ev[], uint16_t nb_events, \
uint64_t timeout_ticks) \
diff --git a/drivers/event/cnxk/cn9k_worker_deq_ca.c b/drivers/event/cnxk/cn9k_worker_deq_ca.c
index dde8288..6c5325f 100644
--- a/drivers/event/cnxk/cn9k_worker_deq_ca.c
+++ b/drivers/event/cnxk/cn9k_worker_deq_ca.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_deq_ca_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/event/cnxk/cn9k_worker_deq_tmo.c b/drivers/event/cnxk/cn9k_worker_deq_tmo.c
index 9713d1e..b41a590 100644
--- a/drivers/event/cnxk/cn9k_worker_deq_tmo.c
+++ b/drivers/event/cnxk/cn9k_worker_deq_tmo.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_deq_tmo_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/event/cnxk/cn9k_worker_dual_deq.c b/drivers/event/cnxk/cn9k_worker_dual_deq.c
index 709fa2d..440b66e 100644
--- a/drivers/event/cnxk/cn9k_worker_dual_deq.c
+++ b/drivers/event/cnxk/cn9k_worker_dual_deq.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c b/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c
index d50e1cf..4d913f9 100644
--- a/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c
+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_burst.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_burst_##name( \
void *port, struct rte_event ev[], uint16_t nb_events, \
uint64_t timeout_ticks) \
diff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c b/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c
index 26cc60f..74116a9 100644
--- a/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c
+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_ca.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_ca_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c b/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c
index a0508fd..78a4b3d 100644
--- a/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c
+++ b/drivers/event/cnxk/cn9k_worker_dual_deq_tmo.c
@@ -6,7 +6,7 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_hot cn9k_sso_hws_dual_deq_tmo_##name( \
void *port, struct rte_event *ev, uint64_t timeout_ticks) \
{ \
diff --git a/drivers/net/cnxk/cn9k_rx.c b/drivers/net/cnxk/cn9k_rx.c
index 7d9f1bd..5c4387e 100644
--- a/drivers/net/cnxk/cn9k_rx.c
+++ b/drivers/net/cnxk/cn9k_rx.c
@@ -5,7 +5,7 @@
#include "cn9k_ethdev.h"
#include "cn9k_rx.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name( \
void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \
{ \
@@ -17,12 +17,13 @@ NIX_RX_FASTPATH_MODES
static inline void
pick_rx_func(struct rte_eth_dev *eth_dev,
- const eth_rx_burst_t rx_burst[2][2][2][2][2][2])
+ const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2])
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
/* [TSP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */
eth_dev->rx_pkt_burst = rx_burst
+ [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)]
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]
[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
@@ -38,33 +39,33 @@ cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
- const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_##name,
+ const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_mseg_##name,
+ const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_mseg_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_##name,
+ const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_##name,
NIX_RX_FASTPATH_MODES
#undef R
};
- const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2] = {
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
- [f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_mseg_##name,
+ const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = {
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
+ [f6][f5][f4][f3][f2][f1][f0] = cn9k_nix_recv_pkts_vec_mseg_##name,
NIX_RX_FASTPATH_MODES
#undef R
@@ -73,7 +74,7 @@ cn9k_eth_set_rx_function(struct rte_eth_dev *eth_dev)
/* Copy multi seg version with no offload for tear down sequence */
if (rte_eal_process_type() == RTE_PROC_PRIMARY)
dev->rx_pkt_burst_no_offload =
- nix_eth_rx_burst_mseg[0][0][0][0][0][0];
+ nix_eth_rx_burst_mseg[0][0][0][0][0][0][0];
if (dev->scalar_ena) {
if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h
index 59545af..bdedeab 100644
--- a/drivers/net/cnxk/cn9k_rx.h
+++ b/drivers/net/cnxk/cn9k_rx.h
@@ -166,24 +166,104 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf,
mbuf->next = NULL;
}
+static __rte_always_inline uint64_t
+nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,
+ uintptr_t sa_base, uint64_t *rearm_val, uint16_t *len)
+{
+ uintptr_t res_sg0 = ((uintptr_t)cq + ROC_ONF_IPSEC_INB_RES_OFF - 8);
+ const union nix_rx_parse_u *rx =
+ (const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
+ struct cn9k_inb_priv_data *sa_priv;
+ struct roc_onf_ipsec_inb_sa *sa;
+ uint8_t lcptr = rx->lcptr;
+ struct rte_ipv4_hdr *ipv4;
+ uint16_t data_off, res;
+ uint32_t spi_mask;
+ uint32_t spi;
+ uintptr_t data;
+ __uint128_t dw;
+ uint8_t sa_w;
+
+ res = *(uint64_t *)(res_sg0 + 8);
+ data_off = *rearm_val & (BIT_ULL(16) - 1);
+ data = (uintptr_t)m->buf_addr;
+ data += data_off;
+
+ rte_prefetch0((void *)data);
+
+ if (unlikely(res != (CPT_COMP_GOOD | ROC_IE_ONF_UCC_SUCCESS << 8)))
+ return PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED;
+
+ data += lcptr;
+ /* 20 bits of tag would have the SPI */
+ spi = cq->tag & CNXK_ETHDEV_SPI_TAG_MASK;
+
+ /* Get SA */
+ sa_w = sa_base & (ROC_NIX_INL_SA_BASE_ALIGN - 1);
+ sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1);
+ spi_mask = (1ULL << sa_w) - 1;
+ sa = roc_nix_inl_onf_ipsec_inb_sa(sa_base, spi & spi_mask);
+
+ /* Update dynamic field with userdata */
+ sa_priv = roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(sa);
+ dw = *(__uint128_t *)sa_priv;
+ *rte_security_dynfield(m) = (uint64_t)dw;
+
+ /* Get total length from IPv4 header. We can assume only IPv4 */
+ ipv4 = (struct rte_ipv4_hdr *)(data + ROC_ONF_IPSEC_INB_SPI_SEQ_SZ +
+ ROC_ONF_IPSEC_INB_MAX_L2_SZ);
+
+ /* Update data offset */
+ data_off += (ROC_ONF_IPSEC_INB_SPI_SEQ_SZ +
+ ROC_ONF_IPSEC_INB_MAX_L2_SZ);
+ *rearm_val = *rearm_val & ~(BIT_ULL(16) - 1);
+ *rearm_val |= data_off;
+
+ *len = rte_be_to_cpu_16(ipv4->total_length) + lcptr;
+ return PKT_RX_SEC_OFFLOAD;
+}
+
static __rte_always_inline void
cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
struct rte_mbuf *mbuf, const void *lookup_mem,
- const uint64_t val, const uint16_t flag)
+ uint64_t val, const uint16_t flag)
{
const union nix_rx_parse_u *rx =
(const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
- const uint16_t len = rx->cn9k.pkt_lenm1 + 1;
+ uint16_t len = rx->cn9k.pkt_lenm1 + 1;
const uint64_t w1 = *(const uint64_t *)rx;
+ uint32_t packet_type;
uint64_t ol_flags = 0;
/* Mark mempool obj as "get" as it is alloc'ed by NIX */
__mempool_check_cookies(mbuf->pool, (void **)&mbuf, 1, 1);
if (flag & NIX_RX_OFFLOAD_PTYPE_F)
- mbuf->packet_type = nix_ptype_get(lookup_mem, w1);
+ packet_type = nix_ptype_get(lookup_mem, w1);
else
- mbuf->packet_type = 0;
+ packet_type = 0;
+
+ if ((flag & NIX_RX_OFFLOAD_SECURITY_F) &&
+ cq->cqe_type == NIX_XQE_TYPE_RX_IPSECH) {
+ uint16_t port = val >> 48;
+ uintptr_t sa_base;
+
+ /* Get SA Base from lookup mem */
+ sa_base = cnxk_nix_sa_base_get(port, lookup_mem);
+
+ ol_flags |= nix_rx_sec_mbuf_update(cq, mbuf, sa_base, &val,
+ &len);
+
+ /* Only Tunnel inner IPv4 is supported */
+ packet_type = (packet_type &
+ ~(RTE_PTYPE_L3_MASK | RTE_PTYPE_TUNNEL_MASK));
+ packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ mbuf->packet_type = packet_type;
+ goto skip_parse;
+ }
+
+ if (flag & NIX_RX_OFFLOAD_PTYPE_F)
+ mbuf->packet_type = packet_type;
if (flag & NIX_RX_OFFLOAD_RSS_F) {
mbuf->hash.rss = tag;
@@ -193,6 +273,7 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
if (flag & NIX_RX_OFFLOAD_CHECKSUM_F)
ol_flags |= nix_rx_olflags_get(lookup_mem, w1);
+skip_parse:
if (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) {
if (rx->cn9k.vtag0_gone) {
ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
@@ -208,11 +289,12 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
ol_flags =
nix_update_match_id(rx->cn9k.match_id, ol_flags, mbuf);
- mbuf->ol_flags = ol_flags;
mbuf->pkt_len = len;
mbuf->data_len = len;
*(uint64_t *)(&mbuf->rearm_data) = val;
+ mbuf->ol_flags = ol_flags;
+
if (flag & NIX_RX_MULTI_SEG_F)
nix_cqe_xtract_mseg(rx, mbuf, val, flag);
else
@@ -670,98 +752,268 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
#define MARK_F NIX_RX_OFFLOAD_MARK_UPDATE_F
#define TS_F NIX_RX_OFFLOAD_TSTAMP_F
#define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F
+#define R_SEC_F NIX_RX_OFFLOAD_SECURITY_F
-/* [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */
+/* [R_SEC_F] [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */
#define NIX_RX_FASTPATH_MODES \
-R(no_offload, 0, 0, 0, 0, 0, 0, NIX_RX_OFFLOAD_NONE) \
-R(rss, 0, 0, 0, 0, 0, 1, RSS_F) \
-R(ptype, 0, 0, 0, 0, 1, 0, PTYPE_F) \
-R(ptype_rss, 0, 0, 0, 0, 1, 1, PTYPE_F | RSS_F) \
-R(cksum, 0, 0, 0, 1, 0, 0, CKSUM_F) \
-R(cksum_rss, 0, 0, 0, 1, 0, 1, CKSUM_F | RSS_F) \
-R(cksum_ptype, 0, 0, 0, 1, 1, 0, CKSUM_F | PTYPE_F) \
-R(cksum_ptype_rss, 0, 0, 0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F) \
-R(mark, 0, 0, 1, 0, 0, 0, MARK_F) \
-R(mark_rss, 0, 0, 1, 0, 0, 1, MARK_F | RSS_F) \
-R(mark_ptype, 0, 0, 1, 0, 1, 0, MARK_F | PTYPE_F) \
-R(mark_ptype_rss, 0, 0, 1, 0, 1, 1, MARK_F | PTYPE_F | RSS_F) \
-R(mark_cksum, 0, 0, 1, 1, 0, 0, MARK_F | CKSUM_F) \
-R(mark_cksum_rss, 0, 0, 1, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \
-R(mark_cksum_ptype, 0, 0, 1, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F) \
-R(mark_cksum_ptype_rss, 0, 0, 1, 1, 1, 1, \
- MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(ts, 0, 1, 0, 0, 0, 0, TS_F) \
-R(ts_rss, 0, 1, 0, 0, 0, 1, TS_F | RSS_F) \
-R(ts_ptype, 0, 1, 0, 0, 1, 0, TS_F | PTYPE_F) \
-R(ts_ptype_rss, 0, 1, 0, 0, 1, 1, TS_F | PTYPE_F | RSS_F) \
-R(ts_cksum, 0, 1, 0, 1, 0, 0, TS_F | CKSUM_F) \
-R(ts_cksum_rss, 0, 1, 0, 1, 0, 1, TS_F | CKSUM_F | RSS_F) \
-R(ts_cksum_ptype, 0, 1, 0, 1, 1, 0, TS_F | CKSUM_F | PTYPE_F) \
-R(ts_cksum_ptype_rss, 0, 1, 0, 1, 1, 1, \
- TS_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(ts_mark, 0, 1, 1, 0, 0, 0, TS_F | MARK_F) \
-R(ts_mark_rss, 0, 1, 1, 0, 0, 1, TS_F | MARK_F | RSS_F) \
-R(ts_mark_ptype, 0, 1, 1, 0, 1, 0, TS_F | MARK_F | PTYPE_F) \
-R(ts_mark_ptype_rss, 0, 1, 1, 0, 1, 1, \
- TS_F | MARK_F | PTYPE_F | RSS_F) \
-R(ts_mark_cksum, 0, 1, 1, 1, 0, 0, TS_F | MARK_F | CKSUM_F) \
-R(ts_mark_cksum_rss, 0, 1, 1, 1, 0, 1, \
- TS_F | MARK_F | CKSUM_F | RSS_F) \
-R(ts_mark_cksum_ptype, 0, 1, 1, 1, 1, 0, \
- TS_F | MARK_F | CKSUM_F | PTYPE_F) \
-R(ts_mark_cksum_ptype_rss, 0, 1, 1, 1, 1, 1, \
- TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(vlan, 1, 0, 0, 0, 0, 0, RX_VLAN_F) \
-R(vlan_rss, 1, 0, 0, 0, 0, 1, RX_VLAN_F | RSS_F) \
-R(vlan_ptype, 1, 0, 0, 0, 1, 0, RX_VLAN_F | PTYPE_F) \
-R(vlan_ptype_rss, 1, 0, 0, 0, 1, 1, RX_VLAN_F | PTYPE_F | RSS_F) \
-R(vlan_cksum, 1, 0, 0, 1, 0, 0, RX_VLAN_F | CKSUM_F) \
-R(vlan_cksum_rss, 1, 0, 0, 1, 0, 1, RX_VLAN_F | CKSUM_F | RSS_F) \
-R(vlan_cksum_ptype, 1, 0, 0, 1, 1, 0, \
- RX_VLAN_F | CKSUM_F | PTYPE_F) \
-R(vlan_cksum_ptype_rss, 1, 0, 0, 1, 1, 1, \
- RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(vlan_mark, 1, 0, 1, 0, 0, 0, RX_VLAN_F | MARK_F) \
-R(vlan_mark_rss, 1, 0, 1, 0, 0, 1, RX_VLAN_F | MARK_F | RSS_F) \
-R(vlan_mark_ptype, 1, 0, 1, 0, 1, 0, RX_VLAN_F | MARK_F | PTYPE_F)\
-R(vlan_mark_ptype_rss, 1, 0, 1, 0, 1, 1, \
- RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \
-R(vlan_mark_cksum, 1, 0, 1, 1, 0, 0, RX_VLAN_F | MARK_F | CKSUM_F)\
-R(vlan_mark_cksum_rss, 1, 0, 1, 1, 0, 1, \
- RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \
-R(vlan_mark_cksum_ptype, 1, 0, 1, 1, 1, 0, \
- RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \
-R(vlan_mark_cksum_ptype_rss, 1, 0, 1, 1, 1, 1, \
- RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(vlan_ts, 1, 1, 0, 0, 0, 0, RX_VLAN_F | TS_F) \
-R(vlan_ts_rss, 1, 1, 0, 0, 0, 1, RX_VLAN_F | TS_F | RSS_F) \
-R(vlan_ts_ptype, 1, 1, 0, 0, 1, 0, RX_VLAN_F | TS_F | PTYPE_F) \
-R(vlan_ts_ptype_rss, 1, 1, 0, 0, 1, 1, \
- RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \
-R(vlan_ts_cksum, 1, 1, 0, 1, 0, 0, RX_VLAN_F | TS_F | CKSUM_F) \
-R(vlan_ts_cksum_rss, 1, 1, 0, 1, 0, 1, \
- RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \
-R(vlan_ts_cksum_ptype, 1, 1, 0, 1, 1, 0, \
- RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \
-R(vlan_ts_cksum_ptype_rss, 1, 1, 0, 1, 1, 1, \
- RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \
-R(vlan_ts_mark, 1, 1, 1, 0, 0, 0, RX_VLAN_F | TS_F | MARK_F) \
-R(vlan_ts_mark_rss, 1, 1, 1, 0, 0, 1, \
- RX_VLAN_F | TS_F | MARK_F | RSS_F) \
-R(vlan_ts_mark_ptype, 1, 1, 1, 0, 1, 0, \
- RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \
-R(vlan_ts_mark_ptype_rss, 1, 1, 1, 0, 1, 1, \
- RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \
-R(vlan_ts_mark_cksum, 1, 1, 1, 1, 0, 0, \
- RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \
-R(vlan_ts_mark_cksum_rss, 1, 1, 1, 1, 0, 1, \
- RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \
-R(vlan_ts_mark_cksum_ptype, 1, 1, 1, 1, 1, 0, \
- RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \
-R(vlan_ts_mark_cksum_ptype_rss, 1, 1, 1, 1, 1, 1, \
- RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)
+R(no_offload, 0, 0, 0, 0, 0, 0, 0, \
+ NIX_RX_OFFLOAD_NONE) \
+R(rss, 0, 0, 0, 0, 0, 0, 1, \
+ RSS_F) \
+R(ptype, 0, 0, 0, 0, 0, 1, 0, \
+ PTYPE_F) \
+R(ptype_rss, 0, 0, 0, 0, 0, 1, 1, \
+ PTYPE_F | RSS_F) \
+R(cksum, 0, 0, 0, 0, 1, 0, 0, \
+ CKSUM_F) \
+R(cksum_rss, 0, 0, 0, 0, 1, 0, 1, \
+ CKSUM_F | RSS_F) \
+R(cksum_ptype, 0, 0, 0, 0, 1, 1, 0, \
+ CKSUM_F | PTYPE_F) \
+R(cksum_ptype_rss, 0, 0, 0, 0, 1, 1, 1, \
+ CKSUM_F | PTYPE_F | RSS_F) \
+R(mark, 0, 0, 0, 1, 0, 0, 0, \
+ MARK_F) \
+R(mark_rss, 0, 0, 0, 1, 0, 0, 1, \
+ MARK_F | RSS_F) \
+R(mark_ptype, 0, 0, 0, 1, 0, 1, 0, \
+ MARK_F | PTYPE_F) \
+R(mark_ptype_rss, 0, 0, 0, 1, 0, 1, 1, \
+ MARK_F | PTYPE_F | RSS_F) \
+R(mark_cksum, 0, 0, 0, 1, 1, 0, 0, \
+ MARK_F | CKSUM_F) \
+R(mark_cksum_rss, 0, 0, 0, 1, 1, 0, 1, \
+ MARK_F | CKSUM_F | RSS_F) \
+R(mark_cksum_ptype, 0, 0, 0, 1, 1, 1, 0, \
+ MARK_F | CKSUM_F | PTYPE_F) \
+R(mark_cksum_ptype_rss, 0, 0, 0, 1, 1, 1, 1, \
+ MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(ts, 0, 0, 1, 0, 0, 0, 0, \
+ TS_F) \
+R(ts_rss, 0, 0, 1, 0, 0, 0, 1, \
+ TS_F | RSS_F) \
+R(ts_ptype, 0, 0, 1, 0, 0, 1, 0, \
+ TS_F | PTYPE_F) \
+R(ts_ptype_rss, 0, 0, 1, 0, 0, 1, 1, \
+ TS_F | PTYPE_F | RSS_F) \
+R(ts_cksum, 0, 0, 1, 0, 1, 0, 0, \
+ TS_F | CKSUM_F) \
+R(ts_cksum_rss, 0, 0, 1, 0, 1, 0, 1, \
+ TS_F | CKSUM_F | RSS_F) \
+R(ts_cksum_ptype, 0, 0, 1, 0, 1, 1, 0, \
+ TS_F | CKSUM_F | PTYPE_F) \
+R(ts_cksum_ptype_rss, 0, 0, 1, 0, 1, 1, 1, \
+ TS_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(ts_mark, 0, 0, 1, 1, 0, 0, 0, \
+ TS_F | MARK_F) \
+R(ts_mark_rss, 0, 0, 1, 1, 0, 0, 1, \
+ TS_F | MARK_F | RSS_F) \
+R(ts_mark_ptype, 0, 0, 1, 1, 0, 1, 0, \
+ TS_F | MARK_F | PTYPE_F) \
+R(ts_mark_ptype_rss, 0, 0, 1, 1, 0, 1, 1, \
+ TS_F | MARK_F | PTYPE_F | RSS_F) \
+R(ts_mark_cksum, 0, 0, 1, 1, 1, 0, 0, \
+ TS_F | MARK_F | CKSUM_F) \
+R(ts_mark_cksum_rss, 0, 0, 1, 1, 1, 0, 1, \
+ TS_F | MARK_F | CKSUM_F | RSS_F) \
+R(ts_mark_cksum_ptype, 0, 0, 1, 1, 1, 1, 0, \
+ TS_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(ts_mark_cksum_ptype_rss, 0, 0, 1, 1, 1, 1, 1, \
+ TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(vlan, 0, 1, 0, 0, 0, 0, 0, \
+ RX_VLAN_F) \
+R(vlan_rss, 0, 1, 0, 0, 0, 0, 1, \
+ RX_VLAN_F | RSS_F) \
+R(vlan_ptype, 0, 1, 0, 0, 0, 1, 0, \
+ RX_VLAN_F | PTYPE_F) \
+R(vlan_ptype_rss, 0, 1, 0, 0, 0, 1, 1, \
+ RX_VLAN_F | PTYPE_F | RSS_F) \
+R(vlan_cksum, 0, 1, 0, 0, 1, 0, 0, \
+ RX_VLAN_F | CKSUM_F) \
+R(vlan_cksum_rss, 0, 1, 0, 0, 1, 0, 1, \
+ RX_VLAN_F | CKSUM_F | RSS_F) \
+R(vlan_cksum_ptype, 0, 1, 0, 0, 1, 1, 0, \
+ RX_VLAN_F | CKSUM_F | PTYPE_F) \
+R(vlan_cksum_ptype_rss, 0, 1, 0, 0, 1, 1, 1, \
+ RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(vlan_mark, 0, 1, 0, 1, 0, 0, 0, \
+ RX_VLAN_F | MARK_F) \
+R(vlan_mark_rss, 0, 1, 0, 1, 0, 0, 1, \
+ RX_VLAN_F | MARK_F | RSS_F) \
+R(vlan_mark_ptype, 0, 1, 0, 1, 0, 1, 0, \
+ RX_VLAN_F | MARK_F | PTYPE_F) \
+R(vlan_mark_ptype_rss, 0, 1, 0, 1, 0, 1, 1, \
+ RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \
+R(vlan_mark_cksum, 0, 1, 0, 1, 1, 0, 0, \
+ RX_VLAN_F | MARK_F | CKSUM_F) \
+R(vlan_mark_cksum_rss, 0, 1, 0, 1, 1, 0, 1, \
+ RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \
+R(vlan_mark_cksum_ptype, 0, 1, 0, 1, 1, 1, 0, \
+ RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(vlan_mark_cksum_ptype_rss, 0, 1, 0, 1, 1, 1, 1, \
+ RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(vlan_ts, 0, 1, 1, 0, 0, 0, 0, \
+ RX_VLAN_F | TS_F) \
+R(vlan_ts_rss, 0, 1, 1, 0, 0, 0, 1, \
+ RX_VLAN_F | TS_F | RSS_F) \
+R(vlan_ts_ptype, 0, 1, 1, 0, 0, 1, 0, \
+ RX_VLAN_F | TS_F | PTYPE_F) \
+R(vlan_ts_ptype_rss, 0, 1, 1, 0, 0, 1, 1, \
+ RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \
+R(vlan_ts_cksum, 0, 1, 1, 0, 1, 0, 0, \
+ RX_VLAN_F | TS_F | CKSUM_F) \
+R(vlan_ts_cksum_rss, 0, 1, 1, 0, 1, 0, 1, \
+ RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \
+R(vlan_ts_cksum_ptype, 0, 1, 1, 0, 1, 1, 0, \
+ RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \
+R(vlan_ts_cksum_ptype_rss, 0, 1, 1, 0, 1, 1, 1, \
+ RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(vlan_ts_mark, 0, 1, 1, 1, 0, 0, 0, \
+ RX_VLAN_F | TS_F | MARK_F) \
+R(vlan_ts_mark_rss, 0, 1, 1, 1, 0, 0, 1, \
+ RX_VLAN_F | TS_F | MARK_F | RSS_F) \
+R(vlan_ts_mark_ptype, 0, 1, 1, 1, 0, 1, 0, \
+ RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \
+R(vlan_ts_mark_ptype_rss, 0, 1, 1, 1, 0, 1, 1, \
+ RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \
+R(vlan_ts_mark_cksum, 0, 1, 1, 1, 1, 0, 0, \
+ RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \
+R(vlan_ts_mark_cksum_rss, 0, 1, 1, 1, 1, 0, 1, \
+ RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \
+R(vlan_ts_mark_cksum_ptype, 0, 1, 1, 1, 1, 1, 0, \
+ RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(vlan_ts_mark_cksum_ptype_rss, 0, 1, 1, 1, 1, 1, 1, \
+ RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec, 1, 0, 0, 0, 0, 0, 0, \
+ R_SEC_F) \
+R(sec_rss, 1, 0, 0, 0, 0, 0, 1, \
+ RSS_F) \
+R(sec_ptype, 1, 0, 0, 0, 0, 1, 0, \
+ R_SEC_F | PTYPE_F) \
+R(sec_ptype_rss, 1, 0, 0, 0, 0, 1, 1, \
+ R_SEC_F | PTYPE_F | RSS_F) \
+R(sec_cksum, 1, 0, 0, 0, 1, 0, 0, \
+ R_SEC_F | CKSUM_F) \
+R(sec_cksum_rss, 1, 0, 0, 0, 1, 0, 1, \
+ R_SEC_F | CKSUM_F | RSS_F) \
+R(sec_cksum_ptype, 1, 0, 0, 0, 1, 1, 0, \
+ R_SEC_F | CKSUM_F | PTYPE_F) \
+R(sec_cksum_ptype_rss, 1, 0, 0, 0, 1, 1, 1, \
+ R_SEC_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_mark, 1, 0, 0, 1, 0, 0, 0, \
+ R_SEC_F | MARK_F) \
+R(sec_mark_rss, 1, 0, 0, 1, 0, 0, 1, \
+ R_SEC_F | MARK_F | RSS_F) \
+R(sec_mark_ptype, 1, 0, 0, 1, 0, 1, 0, \
+ R_SEC_F | MARK_F | PTYPE_F) \
+R(sec_mark_ptype_rss, 1, 0, 0, 1, 0, 1, 1, \
+ R_SEC_F | MARK_F | PTYPE_F | RSS_F) \
+R(sec_mark_cksum, 1, 0, 0, 1, 1, 0, 0, \
+ R_SEC_F | MARK_F | CKSUM_F) \
+R(sec_mark_cksum_rss, 1, 0, 0, 1, 1, 0, 1, \
+ R_SEC_F | MARK_F | CKSUM_F | RSS_F) \
+R(sec_mark_cksum_ptype, 1, 0, 0, 1, 1, 1, 0, \
+ R_SEC_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(sec_mark_cksum_ptype_rss, 1, 0, 0, 1, 1, 1, 1, \
+ R_SEC_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_ts, 1, 0, 1, 0, 0, 0, 0, \
+ R_SEC_F | TS_F) \
+R(sec_ts_rss, 1, 0, 1, 0, 0, 0, 1, \
+ R_SEC_F | TS_F | RSS_F) \
+R(sec_ts_ptype, 1, 0, 1, 0, 0, 1, 0, \
+ R_SEC_F | TS_F | PTYPE_F) \
+R(sec_ts_ptype_rss, 1, 0, 1, 0, 0, 1, 1, \
+ R_SEC_F | TS_F | PTYPE_F | RSS_F) \
+R(sec_ts_cksum, 1, 0, 1, 0, 1, 0, 0, \
+ R_SEC_F | TS_F | CKSUM_F) \
+R(sec_ts_cksum_rss, 1, 0, 1, 0, 1, 0, 1, \
+ R_SEC_F | TS_F | CKSUM_F | RSS_F) \
+R(sec_ts_cksum_ptype, 1, 0, 1, 0, 1, 1, 0, \
+ R_SEC_F | TS_F | CKSUM_F | PTYPE_F) \
+R(sec_ts_cksum_ptype_rss, 1, 0, 1, 0, 1, 1, 1, \
+ R_SEC_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_ts_mark, 1, 0, 1, 1, 0, 0, 0, \
+ R_SEC_F | TS_F | MARK_F) \
+R(sec_ts_mark_rss, 1, 0, 1, 1, 0, 0, 1, \
+ R_SEC_F | TS_F | MARK_F | RSS_F) \
+R(sec_ts_mark_ptype, 1, 0, 1, 1, 0, 1, 0, \
+ R_SEC_F | TS_F | MARK_F | PTYPE_F) \
+R(sec_ts_mark_ptype_rss, 1, 0, 1, 1, 0, 1, 1, \
+ R_SEC_F | TS_F | MARK_F | PTYPE_F | RSS_F) \
+R(sec_ts_mark_cksum, 1, 0, 1, 1, 1, 0, 0, \
+ R_SEC_F | TS_F | MARK_F | CKSUM_F) \
+R(sec_ts_mark_cksum_rss, 1, 0, 1, 1, 1, 0, 1, \
+ R_SEC_F | TS_F | MARK_F | CKSUM_F | RSS_F) \
+R(sec_ts_mark_cksum_ptype, 1, 0, 1, 1, 1, 1, 0, \
+ R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(sec_ts_mark_cksum_ptype_rss, 1, 0, 1, 1, 1, 1, 1, \
+ R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_vlan, 1, 1, 0, 0, 0, 0, 0, \
+ R_SEC_F | RX_VLAN_F) \
+R(sec_vlan_rss, 1, 1, 0, 0, 0, 0, 1, \
+ R_SEC_F | RX_VLAN_F | RSS_F) \
+R(sec_vlan_ptype, 1, 1, 0, 0, 0, 1, 0, \
+ R_SEC_F | RX_VLAN_F | PTYPE_F) \
+R(sec_vlan_ptype_rss, 1, 1, 0, 0, 0, 1, 1, \
+ R_SEC_F | RX_VLAN_F | PTYPE_F | RSS_F) \
+R(sec_vlan_cksum, 1, 1, 0, 0, 1, 0, 0, \
+ R_SEC_F | RX_VLAN_F | CKSUM_F) \
+R(sec_vlan_cksum_rss, 1, 1, 0, 0, 1, 0, 1, \
+ R_SEC_F | RX_VLAN_F | CKSUM_F | RSS_F) \
+R(sec_vlan_cksum_ptype, 1, 1, 0, 0, 1, 1, 0, \
+ R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F) \
+R(sec_vlan_cksum_ptype_rss, 1, 1, 0, 0, 1, 1, 1, \
+ R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_vlan_mark, 1, 1, 0, 1, 0, 0, 0, \
+ R_SEC_F | RX_VLAN_F | MARK_F) \
+R(sec_vlan_mark_rss, 1, 1, 0, 1, 0, 0, 1, \
+ R_SEC_F | RX_VLAN_F | MARK_F | RSS_F) \
+R(sec_vlan_mark_ptype, 1, 1, 0, 1, 0, 1, 0, \
+ R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F) \
+R(sec_vlan_mark_ptype_rss, 1, 1, 0, 1, 0, 1, 1, \
+ R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \
+R(sec_vlan_mark_cksum, 1, 1, 0, 1, 1, 0, 0, \
+ R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F) \
+R(sec_vlan_mark_cksum_rss, 1, 1, 0, 1, 1, 0, 1, \
+ R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \
+R(sec_vlan_mark_cksum_ptype, 1, 1, 0, 1, 1, 1, 0, \
+ R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(sec_vlan_mark_cksum_ptype_rss, 1, 1, 0, 1, 1, 1, 1, \
+ R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_vlan_ts, 1, 1, 1, 0, 0, 0, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F) \
+R(sec_vlan_ts_rss, 1, 1, 1, 0, 0, 0, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | RSS_F) \
+R(sec_vlan_ts_ptype, 1, 1, 1, 0, 0, 1, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F) \
+R(sec_vlan_ts_ptype_rss, 1, 1, 1, 0, 0, 1, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \
+R(sec_vlan_ts_cksum, 1, 1, 1, 0, 1, 0, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F) \
+R(sec_vlan_ts_cksum_rss, 1, 1, 1, 0, 1, 0, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \
+R(sec_vlan_ts_cksum_ptype, 1, 1, 1, 0, 1, 1, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \
+R(sec_vlan_ts_cksum_ptype_rss, 1, 1, 1, 0, 1, 1, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \
+R(sec_vlan_ts_mark, 1, 1, 1, 1, 0, 0, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F) \
+R(sec_vlan_ts_mark_rss, 1, 1, 1, 1, 0, 0, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | RSS_F) \
+R(sec_vlan_ts_mark_ptype, 1, 1, 1, 1, 0, 1, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \
+R(sec_vlan_ts_mark_ptype_rss, 1, 1, 1, 1, 0, 1, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \
+R(sec_vlan_ts_mark_cksum, 1, 1, 1, 1, 1, 0, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \
+R(sec_vlan_ts_mark_cksum_rss, 1, 1, 1, 1, 1, 0, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \
+R(sec_vlan_ts_mark_cksum_ptype, 1, 1, 1, 1, 1, 1, 0, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \
+R(sec_vlan_ts_mark_cksum_ptype_rss, 1, 1, 1, 1, 1, 1, 1, \
+ R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_##name( \
void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \
\
diff --git a/drivers/net/cnxk/cn9k_rx_mseg.c b/drivers/net/cnxk/cn9k_rx_mseg.c
index d7e19b1..06509e8 100644
--- a/drivers/net/cnxk/cn9k_rx_mseg.c
+++ b/drivers/net/cnxk/cn9k_rx_mseg.c
@@ -5,7 +5,7 @@
#include "cn9k_ethdev.h"
#include "cn9k_rx.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_mseg_##name( \
void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \
{ \
diff --git a/drivers/net/cnxk/cn9k_rx_vec.c b/drivers/net/cnxk/cn9k_rx_vec.c
index ef5f771..c96f61c 100644
--- a/drivers/net/cnxk/cn9k_rx_vec.c
+++ b/drivers/net/cnxk/cn9k_rx_vec.c
@@ -5,7 +5,7 @@
#include "cn9k_ethdev.h"
#include "cn9k_rx.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_##name( \
void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \
{ \
diff --git a/drivers/net/cnxk/cn9k_rx_vec_mseg.c b/drivers/net/cnxk/cn9k_rx_vec_mseg.c
index e46d8a4..938b1c0 100644
--- a/drivers/net/cnxk/cn9k_rx_vec_mseg.c
+++ b/drivers/net/cnxk/cn9k_rx_vec_mseg.c
@@ -5,7 +5,7 @@
#include "cn9k_ethdev.h"
#include "cn9k_rx.h"
-#define R(name, f5, f4, f3, f2, f1, f0, flags) \
+#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \
uint16_t __rte_noinline __rte_hot cn9k_nix_recv_pkts_vec_mseg_##name( \
void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \
{ \
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 5ae791f..cfdc493 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -130,6 +130,9 @@
/* Subtype from inline outbound error event */
#define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL
+/* SPI will be in 20 bits of tag */
+#define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL
+
struct cnxk_fc_cfg {
enum rte_eth_fc_mode mode;
uint8_t rx_pause;
--
2.8.4
next prev parent reply other threads:[~2021-09-02 2:18 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 2:14 [dpdk-dev] [PATCH 00/27] net/cnxk: support for inline ipsec Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 01/27] common/cnxk: add security support for cn9k fast path Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 02/27] common/cnxk: add helper API to dump cpt parse header Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 03/27] common/cnxk: allow reuse of SSO API for inline dev Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 04/27] common/cnxk: change nix debug API and queue API interface Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 05/27] common/cnxk: add nix inline device irq API Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 06/27] common/cnxk: add nix inline device init and fini Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 07/27] common/cnxk: add nix inline inbound and outbound support API Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 08/27] common/cnxk: dump cpt lf registers on error intr Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 09/27] common/cnxk: align cpt lf enable/disable sequence Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 10/27] common/cnxk: restore nix sqb pool limit before destroy Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 11/27] common/cnxk: add cq enable support in nix Tx path Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 12/27] common/cnxk: setup aura bp conf based on nix Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 13/27] common/cnxk: add anti-replay check implementation for cn9k Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 14/27] common/cnxk: add inline IPsec support in rte flow Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 15/27] net/cnxk: add inline security support for cn9k Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 16/27] net/cnxk: add inline security support for cn10k Nithin Dabilpuram
2021-09-02 2:14 ` Nithin Dabilpuram [this message]
2021-09-02 2:14 ` [dpdk-dev] [PATCH 18/27] net/cnxk: add cn9k Tx support for security offload Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 19/27] net/cnxk: add cn10k Rx " Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 20/27] net/cnxk: add cn10k Tx " Nithin Dabilpuram
2021-09-02 2:14 ` [dpdk-dev] [PATCH 21/27] net/cnxk: add cn9k anti replay " Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 22/27] net/cnxk: add cn10k IPsec transport mode support Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 23/27] net/cnxk: update ethertype for mixed IPsec tunnel versions Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 24/27] net/cnxk: allow zero udp6 checksum for non inline device Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 25/27] net/cnxk: add crypto capabilities for AES CBC and HMAC SHA1 Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 26/27] net/cnxk: add devargs for configuring channel mask Nithin Dabilpuram
2021-09-02 2:15 ` [dpdk-dev] [PATCH 27/27] net/cnxk: reflect globally enabled offloads in queue conf Nithin Dabilpuram
2021-09-29 12:44 ` [dpdk-dev] [PATCH 00/27] net/cnxk: support for inline ipsec Jerin Jacob
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 00/28] " Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 01/28] common/cnxk: support cn9k fast path security session Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 02/28] common/cnxk: support CPT parse header dump Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 03/28] common/cnxk: allow reuse of SSO API for inline dev Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 04/28] common/cnxk: change NIX debug API and queue API interface Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 05/28] common/cnxk: support NIX inline device IRQ Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 06/28] common/cnxk: support NIX inline device init and fini Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 07/28] common/cnxk: support NIX inline inbound and outbound setup Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 08/28] common/cnxk: disable CQ drop when inline inbound is enabled Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 09/28] common/cnxk: dump CPT LF registers on error intr Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 10/28] common/cnxk: align CPT LF enable/disable sequence Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 11/28] common/cnxk: restore NIX sqb pool limit before destroy Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 12/28] common/cnxk: add CQ enable support in NIX Tx path Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 13/28] common/cnxk: setup aura BP conf based on nix Nithin Dabilpuram
2021-09-30 17:00 ` [dpdk-dev] [PATCH v2 14/28] common/cnxk: support anti-replay check in SW for cn9k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 15/28] common/cnxk: support inline IPsec rte flow action Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 16/28] net/cnxk: support inline security setup for cn9k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 17/28] net/cnxk: support inline security setup for cn10k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 18/28] net/cnxk: support Rx security offload on cn9k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 19/28] net/cnxk: support Tx " Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 20/28] net/cnxk: support Rx security offload on cn10k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 21/28] net/cnxk: support Tx " Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 22/28] net/cnxk: support IPsec anti replay in cn9k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 23/28] net/cnxk: support IPsec transport mode in cn10k Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 24/28] net/cnxk: update ethertype for mixed IPsec tunnel versions Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 25/28] net/cnxk: allow zero udp6 checksum for non inline device Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 26/28] net/cnxk: add crypto capabilities for AES CBC and HMAC SHA1 Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 27/28] net/cnxk: support configuring channel mask via devargs Nithin Dabilpuram
2021-09-30 17:01 ` [dpdk-dev] [PATCH v2 28/28] net/cnxk: reflect globally enabled offloads in queue conf Nithin Dabilpuram
2021-10-01 5:37 ` [dpdk-dev] [PATCH v2 00/28] net/cnxk: support for inline ipsec Jerin Jacob
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 " Nithin Dabilpuram
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 01/28] common/cnxk: support cn9k fast path security session Nithin Dabilpuram
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 02/28] common/cnxk: support CPT parse header dump Nithin Dabilpuram
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 03/28] common/cnxk: allow reuse of SSO API for inline dev Nithin Dabilpuram
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 04/28] common/cnxk: change NIX debug API and queue API interface Nithin Dabilpuram
2021-10-01 13:39 ` [dpdk-dev] [PATCH v3 05/28] common/cnxk: support NIX inline device IRQ Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 06/28] common/cnxk: support NIX inline device init and fini Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 07/28] common/cnxk: support NIX inline inbound and outbound setup Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 08/28] common/cnxk: disable CQ drop when inline inbound is enabled Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 09/28] common/cnxk: dump CPT LF registers on error intr Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 10/28] common/cnxk: align CPT LF enable/disable sequence Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 11/28] common/cnxk: restore NIX sqb pool limit before destroy Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 12/28] common/cnxk: add CQ enable support in NIX Tx path Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 13/28] common/cnxk: setup aura BP conf based on nix Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 14/28] common/cnxk: support anti-replay check in SW for cn9k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 15/28] common/cnxk: support inline IPsec rte flow action Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 16/28] net/cnxk: support inline security setup for cn9k Nithin Dabilpuram
2021-10-06 16:21 ` Ferruh Yigit
2021-10-06 16:44 ` Nithin Kumar Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 17/28] net/cnxk: support inline security setup for cn10k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 18/28] net/cnxk: support Rx security offload on cn9k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 19/28] net/cnxk: support Tx " Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 20/28] net/cnxk: support Rx security offload on cn10k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 21/28] net/cnxk: support Tx " Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 22/28] net/cnxk: support IPsec anti replay in cn9k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 23/28] net/cnxk: support IPsec transport mode in cn10k Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 24/28] net/cnxk: update ethertype for mixed IPsec tunnel versions Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 25/28] net/cnxk: allow zero udp6 checksum for non inline device Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 26/28] net/cnxk: add crypto capabilities for AES CBC and HMAC SHA1 Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 27/28] net/cnxk: support configuring channel mask via devargs Nithin Dabilpuram
2021-10-01 13:40 ` [dpdk-dev] [PATCH v3 28/28] net/cnxk: reflect globally enabled offloads in queue conf Nithin Dabilpuram
2021-10-02 13:49 ` [dpdk-dev] [PATCH v3 00/28] net/cnxk: support for inline ipsec Jerin Jacob
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