From: Shawn Guo <shawn.guo@linaro.org>
To: Georgi Djakov <djakov@kernel.org>
Cc: AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Yassine Oudjana <y.oudjana@protonmail.com>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
Shawn Guo <shawn.guo@linaro.org>
Subject: [PATCH v2] interconnect: qcom: sdm660: Correct NOC_QOS_PRIORITY shift and mask
Date: Thu, 2 Sep 2021 13:49:15 +0800 [thread overview]
Message-ID: <20210902054915.28689-1-shawn.guo@linaro.org> (raw)
The NOC_QOS_PRIORITY shift and mask do not match what vendor kernel
defines [1]. Correct them per vendor kernel. As the result of
NOC_QOS_PRIORITY_P0_SHIFT being 0, the definition can be dropped and
regmap_update_bits() call on P0 can be simplified a bit.
[1] https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/soc/qcom/msm_bus/msm_bus_noc_adhoc.c?h=LA.UM.8.2.r1-04800-sdm660.0#n37
Fixes: f80a1d414328 ("interconnect: qcom: Add SDM660 interconnect provider driver")
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes for v2:
- Follow Angelo's suggestion to drop NOC_QOS_PRIORITY_P0_SHIFT.
drivers/interconnect/qcom/sdm660.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
index 6fd8e9800218..fb23a5b780a4 100644
--- a/drivers/interconnect/qcom/sdm660.c
+++ b/drivers/interconnect/qcom/sdm660.c
@@ -44,9 +44,9 @@
#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS)
#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
-#define NOC_QOS_PRIORITY_MASK 0xf
+#define NOC_QOS_PRIORITY_P1_MASK 0xc
+#define NOC_QOS_PRIORITY_P0_MASK 0x3
#define NOC_QOS_PRIORITY_P1_SHIFT 0x2
-#define NOC_QOS_PRIORITY_P0_SHIFT 0x3
#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
#define NOC_QOS_MODEn_MASK 0x3
@@ -634,13 +634,12 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
/* Must be updated one at a time, P1 first, P0 last */
val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
- NOC_QOS_PRIORITY_MASK, val);
+ NOC_QOS_PRIORITY_P1_MASK, val);
if (rc)
return rc;
- val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
- NOC_QOS_PRIORITY_MASK, val);
+ NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
}
static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
--
2.17.1
next reply other threads:[~2021-09-02 5:49 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 5:49 Shawn Guo [this message]
2021-09-02 6:57 ` [PATCH v2] interconnect: qcom: sdm660: Correct NOC_QOS_PRIORITY shift and mask AngeloGioacchino Del Regno
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