From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 479B5C4320A for ; Thu, 2 Sep 2021 14:12:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2DC0061057 for ; Thu, 2 Sep 2021 14:12:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345447AbhIBONy (ORCPT ); Thu, 2 Sep 2021 10:13:54 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:49912 "EHLO us-smtp-delivery-124.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345369AbhIBONo (ORCPT ); Thu, 2 Sep 2021 10:13:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1630591963; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=bVLGJjhnuK2Usr0tAcSZ00/YOJ+Y92qvakkwIsnx7M4a/Hb2N5/7QMbHqVg9OJRqaQY5dp wFX2jfEIcIyLMNZuM25DcFta++agqJl5VT7KwAPuwMLIM7FOnJmrRnGxPGUj8P1IkHADps xS0aP9OBp9A5dXZzQG+GqVmNBM8LeGA= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-558-x1Jy_fjrM3qt1CIDB0E41A-1; Thu, 02 Sep 2021 10:12:41 -0400 X-MC-Unique: x1Jy_fjrM3qt1CIDB0E41A-1 Received: by mail-wm1-f72.google.com with SMTP id n16-20020a1c7210000000b002ea2ed60dc6so749613wmc.0 for ; Thu, 02 Sep 2021 07:12:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=N2uxX/WfnMc7ef03VrGj6S+VAOziQY2Am6A9HCxgX28n1LMeT72aFwedypLBhRWLVC EU2QvYpHKDC3VY6r1oL5QcO6hvS8D/0qieuvEPo826L9KqHszFWBxZEKZSVINmkRLG3j Cf8mMv+n3YVlqHagOZemPdhKgPZa1L+3RZlbmJfwbEFoF+8mxKCKIVw8Ob+7dZOnhY3l KyvkYm7lrAX0H4qI+A9DKL0+l8zmFDuna+DbmkbTmua7V1F2tJ0dNDNf5OUegI+OGauY +kcDVy67/bZoiUpUk3aPvhwMYYFpAqcQVLi6werqzTwoDpvpSkmbbJdyDfxieaiUh0hB fAOg== X-Gm-Message-State: AOAM532yOOyNxw8Gltva0liJsRNq9nxWzmaLU2oTtftKwX4dH6yMX5tH wFFXxPK+BK+7dOWJsBqpNGs0SXIiHItEZW+PFnpOfLWc3jRtfC5GFGc/61fAwQkGXRIL/gEyTO6 M6KWXKiArrrxWwqo7JFRe43R3 X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450484wmm.65.1630591960563; Thu, 02 Sep 2021 07:12:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtXz3TEVH3IBGGj1EQWgvfH/dex7qONnxSgYAC6xWL5W99QDZGCYHswtmsZBxRRw6IB0pnsg== X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450340wmm.65.1630591959082; Thu, 02 Sep 2021 07:12:39 -0700 (PDT) Received: from gator (nat-pool-brq-u.redhat.com. [213.175.37.12]) by smtp.gmail.com with ESMTPSA id v62sm1775380wme.21.2021.09.02.07.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 07:12:38 -0700 (PDT) Date: Thu, 2 Sep 2021 16:12:37 +0200 From: Andrew Jones To: Raghavendra Rao Ananta Cc: Paolo Bonzini , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , kvm@vger.kernel.org, Catalin Marinas , Peter Shier , linux-kernel@vger.kernel.org, Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 04/12] KVM: arm64: selftests: Add basic support for arch_timers Message-ID: <20210902141237.vdp7z2gohdh732qs@gator> References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-5-rananta@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210901211412.4171835-5-rananta@google.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 01, 2021 at 09:14:04PM +0000, Raghavendra Rao Ananta wrote: > Add a minimalistic library support to access the virtual timers, > that can be used for simple timing functionalities, such as > introducing delays in the guest. > > Signed-off-by: Raghavendra Rao Ananta > --- > .../kvm/include/aarch64/arch_timer.h | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 tools/testing/selftests/kvm/include/aarch64/arch_timer.h > > diff --git a/tools/testing/selftests/kvm/include/aarch64/arch_timer.h b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > new file mode 100644 > index 000000000000..9df5b63abc47 > --- /dev/null > +++ b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > @@ -0,0 +1,142 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * ARM Generic Timer specific interface > + */ > + > +#ifndef SELFTEST_KVM_ARCH_TIMER_H > +#define SELFTEST_KVM_ARCH_TIMER_H > + > +#include "processor.h" > + > +enum arch_timer { > + VIRTUAL, > + PHYSICAL, > +}; > + > +#define CTL_ENABLE (1 << 0) > +#define CTL_IMASK (1 << 1) > +#define CTL_ISTATUS (1 << 2) > + > +#define msec_to_cycles(msec) \ > + (timer_get_cntfrq() * (uint64_t)(msec) / 1000) > + > +#define usec_to_cycles(usec) \ > + (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) > + > +#define cycles_to_usec(cycles) \ > + ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) > + > +static inline uint32_t timer_get_cntfrq(void) > +{ > + return read_sysreg(cntfrq_el0); > +} > + > +static inline uint64_t timer_get_cntct(enum arch_timer timer) > +{ > + isb(); > + > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntvct_el0); > + case PHYSICAL: > + return read_sysreg(cntpct_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_cval_el0, cval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_cval_el0, cval); Huh, looks like we managed to merge a backwards write_sysreg into kvm selftests. write_sysreg in the kernel and kvm-unit-tests is (value, reg). We should post a patch fixing that before adding more calls to it. > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint64_t timer_get_cval(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_cval_el0); > + case PHYSICAL: > + return read_sysreg(cntp_cval_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_tval(enum arch_timer timer, uint32_t tval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_tval_el0, tval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_tval_el0, tval); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_ctl_el0, ctl); > + break; > + case PHYSICAL: > + write_sysreg(cntp_ctl_el0, ctl); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint32_t timer_get_ctl(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_ctl_el0); > + case PHYSICAL: > + return read_sysreg(cntp_ctl_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} I'll have to look at the test code that uses the above functions, but I wonder if it wouldn't be better to define two test functions, one for vtimer and one for ptimer where the sysreg accesses are direct, rather than all these switched wrappers. > + > +static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) > +{ > + uint64_t now_ct = timer_get_cntct(timer); > + uint64_t next_ct = now_ct + msec_to_cycles(msec); > + > + timer_set_cval(timer, next_ct); > +} > + > +static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) > +{ > + timer_set_tval(timer, msec_to_cycles(msec)); > +} I'll also look at how these wrappers are used, since open coding them may be OK. Thanks, drew > + > +#endif /* SELFTEST_KVM_ARCH_TIMER_H */ > -- > 2.33.0.153.gba50c8fa24-goog > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE17CC432BE for ; Thu, 2 Sep 2021 14:12:54 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 322CF610E5 for ; Thu, 2 Sep 2021 14:12:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 322CF610E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B37EE4B090; Thu, 2 Sep 2021 10:12:53 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@redhat.com Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GxgNWeUNJoTn; Thu, 2 Sep 2021 10:12:49 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DA7E94B13E; Thu, 2 Sep 2021 10:12:49 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D40DF4B133 for ; Thu, 2 Sep 2021 10:12:48 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rLRykN952KyW for ; Thu, 2 Sep 2021 10:12:45 -0400 (EDT) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0E0144B090 for ; Thu, 2 Sep 2021 10:12:45 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1630591964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=eHRKzSnigo/fESSX1Wy6Qvm8MkjaYDUEBlGEZGdiXliel31vJn8mOysbhIPXYGT89aAFx7 WgI8dUAiSWE3njwhNKIdCampINlrH0z0DigCUANopmlxln1RZ+meFjPNUWYr1LuGSzUWux zph8Tia1WZJ1e2YkZ9+KMRxSJq8Y8/0= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-371-I74jQ6dAOTW-PtfTUj1UAA-1; Thu, 02 Sep 2021 10:12:41 -0400 X-MC-Unique: I74jQ6dAOTW-PtfTUj1UAA-1 Received: by mail-wm1-f72.google.com with SMTP id m22-20020a7bca56000000b002e7508f3faeso759748wml.2 for ; Thu, 02 Sep 2021 07:12:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=URsz6P46/LAObVKIh8FFRW/yhqUQ4cx3kd9PzMgtB60wu7nZ/VV0pUDbnkO9Qg44mh zlwZgUpherLw7mM1V1wLHejUYQye33GvFw9LwnKGPrkx/OyQY+FhRM10+KIFqScEKFFp Xtc1r+4aMiM+PjthT3Sqd+OQyrWagEHe1cluPrzpE2inl24EGAqHCkll7skFMqprO6Bb zfgPCEnbjTIg8FgrMR13tyVjBT0AmAgJLPbeTJE4skeGsd6INB+g7KtJKY+Sqcn/owUA QbpJNN0ZIPM8lR5uM4rwb7RVsgyGgnUwwPNR/9WPrV+F8hu2tjOdh3THq4tqAvpJdSYW R7Kg== X-Gm-Message-State: AOAM530IADvGNr7+IQBHF5tgeZoJ/sfyyFu3TWB2zFjXVXmUlLIyNKyR GKK9n/levJgnwn7QmuA9XjxfjoPsoqC2NLWI/fnZBLSJxZL3nOSvlJLmb2Lvre9bNkTCEi5Lpu2 lHLgTbGxqCciU8ytDIfpQ4hFg X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450489wmm.65.1630591960606; Thu, 02 Sep 2021 07:12:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtXz3TEVH3IBGGj1EQWgvfH/dex7qONnxSgYAC6xWL5W99QDZGCYHswtmsZBxRRw6IB0pnsg== X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450340wmm.65.1630591959082; Thu, 02 Sep 2021 07:12:39 -0700 (PDT) Received: from gator (nat-pool-brq-u.redhat.com. [213.175.37.12]) by smtp.gmail.com with ESMTPSA id v62sm1775380wme.21.2021.09.02.07.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 07:12:38 -0700 (PDT) Date: Thu, 2 Sep 2021 16:12:37 +0200 From: Andrew Jones To: Raghavendra Rao Ananta Subject: Re: [PATCH v3 04/12] KVM: arm64: selftests: Add basic support for arch_timers Message-ID: <20210902141237.vdp7z2gohdh732qs@gator> References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-5-rananta@google.com> MIME-Version: 1.0 In-Reply-To: <20210901211412.4171835-5-rananta@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline Cc: kvm@vger.kernel.org, Marc Zyngier , Peter Shier , linux-kernel@vger.kernel.org, Will Deacon , Catalin Marinas , Paolo Bonzini , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, Sep 01, 2021 at 09:14:04PM +0000, Raghavendra Rao Ananta wrote: > Add a minimalistic library support to access the virtual timers, > that can be used for simple timing functionalities, such as > introducing delays in the guest. > > Signed-off-by: Raghavendra Rao Ananta > --- > .../kvm/include/aarch64/arch_timer.h | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 tools/testing/selftests/kvm/include/aarch64/arch_timer.h > > diff --git a/tools/testing/selftests/kvm/include/aarch64/arch_timer.h b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > new file mode 100644 > index 000000000000..9df5b63abc47 > --- /dev/null > +++ b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > @@ -0,0 +1,142 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * ARM Generic Timer specific interface > + */ > + > +#ifndef SELFTEST_KVM_ARCH_TIMER_H > +#define SELFTEST_KVM_ARCH_TIMER_H > + > +#include "processor.h" > + > +enum arch_timer { > + VIRTUAL, > + PHYSICAL, > +}; > + > +#define CTL_ENABLE (1 << 0) > +#define CTL_IMASK (1 << 1) > +#define CTL_ISTATUS (1 << 2) > + > +#define msec_to_cycles(msec) \ > + (timer_get_cntfrq() * (uint64_t)(msec) / 1000) > + > +#define usec_to_cycles(usec) \ > + (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) > + > +#define cycles_to_usec(cycles) \ > + ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) > + > +static inline uint32_t timer_get_cntfrq(void) > +{ > + return read_sysreg(cntfrq_el0); > +} > + > +static inline uint64_t timer_get_cntct(enum arch_timer timer) > +{ > + isb(); > + > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntvct_el0); > + case PHYSICAL: > + return read_sysreg(cntpct_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_cval_el0, cval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_cval_el0, cval); Huh, looks like we managed to merge a backwards write_sysreg into kvm selftests. write_sysreg in the kernel and kvm-unit-tests is (value, reg). We should post a patch fixing that before adding more calls to it. > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint64_t timer_get_cval(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_cval_el0); > + case PHYSICAL: > + return read_sysreg(cntp_cval_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_tval(enum arch_timer timer, uint32_t tval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_tval_el0, tval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_tval_el0, tval); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_ctl_el0, ctl); > + break; > + case PHYSICAL: > + write_sysreg(cntp_ctl_el0, ctl); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint32_t timer_get_ctl(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_ctl_el0); > + case PHYSICAL: > + return read_sysreg(cntp_ctl_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} I'll have to look at the test code that uses the above functions, but I wonder if it wouldn't be better to define two test functions, one for vtimer and one for ptimer where the sysreg accesses are direct, rather than all these switched wrappers. > + > +static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) > +{ > + uint64_t now_ct = timer_get_cntct(timer); > + uint64_t next_ct = now_ct + msec_to_cycles(msec); > + > + timer_set_cval(timer, next_ct); > +} > + > +static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) > +{ > + timer_set_tval(timer, msec_to_cycles(msec)); > +} I'll also look at how these wrappers are used, since open coding them may be OK. Thanks, drew > + > +#endif /* SELFTEST_KVM_ARCH_TIMER_H */ > -- > 2.33.0.153.gba50c8fa24-goog > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52147C432BE for ; Thu, 2 Sep 2021 14:15:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13DCE60F91 for ; Thu, 2 Sep 2021 14:15:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 13DCE60F91 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hHpf0Qh7DEuHGyRl85lWa5277rv7utchafNIeAGE/oo=; b=FGCzJHApWXW/82 he1chRIDjW0pcAGTBoh9NZwVXNz24M7RnalLin9zyhcxMM2j70eGdtRudPBfVRlFid+H3DoSEaR9B wr7pC2lCNOocX1AdbdUdHzJOab45xZNMEKEZ1g+FxYpI4LXWa8cm0gvfZSm0ezfwLLoXuHBc1rPQK Myf9i1UGyGyD1n3WasgPBfMI8ZHO/LGJ1Z0HWmBzlpcCq9yBFSZB3ZpNyxh4sMo5toSnWuvH1jToT 8mxjtmtYUoNzhVzEreiYNXgMmLLSis2A9x0QyPdbDgGTNyFy5+Mrd5Ilus9xBp7Ds4RmlbZ0kVBRJ aqI+LxxRpa3H85iY9vUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mLnSV-009nak-Lb; Thu, 02 Sep 2021 14:12:51 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mLnSQ-009na3-25 for linux-arm-kernel@lists.infradead.org; Thu, 02 Sep 2021 14:12:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1630591964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=eHRKzSnigo/fESSX1Wy6Qvm8MkjaYDUEBlGEZGdiXliel31vJn8mOysbhIPXYGT89aAFx7 WgI8dUAiSWE3njwhNKIdCampINlrH0z0DigCUANopmlxln1RZ+meFjPNUWYr1LuGSzUWux zph8Tia1WZJ1e2YkZ9+KMRxSJq8Y8/0= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-266-KMAq1Sg3MsGgO5hfZNtuCA-1; Thu, 02 Sep 2021 10:12:41 -0400 X-MC-Unique: KMAq1Sg3MsGgO5hfZNtuCA-1 Received: by mail-wm1-f72.google.com with SMTP id w25-20020a1cf6190000b0290252505ddd56so759961wmc.3 for ; Thu, 02 Sep 2021 07:12:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wE6+/Vrhwq4T1/jtKU4o2cvBNu2Pj3FE7J1tJqRcmHM=; b=SgzE906icfSSFIu0NjwtELcvBgVzXEmw0o2kZHNsMEbtdqNusTtz1L4SE5FfSAfsMD QcBnqDtbgdP+ZnBkMvi8trrpv4WfPl7G3SF7UesvRM3S9TAK0KewRm00GLdqr/1iTnVH 9noEsCnDxG2cHUv66odEkWx6Qninhs3DCwlr4ig3ghj13/td/bbsmywm8zEd3Fmq5svB 84fTTGyct4HSV+XBLyqaJZtRl5HqyVH/2IKasoX/nXZ1yp51Eq0ljp3VL1ZsfVBYq1TW vtvK2vmjD0n1nY+AdoCSdJlOzlSms0KkTXeS3kFqIzQQQapbqAg+20fHdNyrZQ+0s0Ux hw0w== X-Gm-Message-State: AOAM530PbRK08kdp/L9Q5yKa34qM4BdVHOQQ1rOkSYX41DL3IjA7hCMj Ur1fudIReMZKBxU9s2bpxnzpTmpZ4cmbgXZW7HzuQ6s/zMkFJ0PUjTCzIeaKtm5wxEJn52J+931 FoIifbk4d+rUjMiyh34arrB7r3yztGfSkptA= X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450486wmm.65.1630591960565; Thu, 02 Sep 2021 07:12:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtXz3TEVH3IBGGj1EQWgvfH/dex7qONnxSgYAC6xWL5W99QDZGCYHswtmsZBxRRw6IB0pnsg== X-Received: by 2002:a1c:2684:: with SMTP id m126mr3450340wmm.65.1630591959082; Thu, 02 Sep 2021 07:12:39 -0700 (PDT) Received: from gator (nat-pool-brq-u.redhat.com. [213.175.37.12]) by smtp.gmail.com with ESMTPSA id v62sm1775380wme.21.2021.09.02.07.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 07:12:38 -0700 (PDT) Date: Thu, 2 Sep 2021 16:12:37 +0200 From: Andrew Jones To: Raghavendra Rao Ananta Cc: Paolo Bonzini , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , kvm@vger.kernel.org, Catalin Marinas , Peter Shier , linux-kernel@vger.kernel.org, Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 04/12] KVM: arm64: selftests: Add basic support for arch_timers Message-ID: <20210902141237.vdp7z2gohdh732qs@gator> References: <20210901211412.4171835-1-rananta@google.com> <20210901211412.4171835-5-rananta@google.com> MIME-Version: 1.0 In-Reply-To: <20210901211412.4171835-5-rananta@google.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210902_071246_231427_D6E5F9FA X-CRM114-Status: GOOD ( 28.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 01, 2021 at 09:14:04PM +0000, Raghavendra Rao Ananta wrote: > Add a minimalistic library support to access the virtual timers, > that can be used for simple timing functionalities, such as > introducing delays in the guest. > > Signed-off-by: Raghavendra Rao Ananta > --- > .../kvm/include/aarch64/arch_timer.h | 142 ++++++++++++++++++ > 1 file changed, 142 insertions(+) > create mode 100644 tools/testing/selftests/kvm/include/aarch64/arch_timer.h > > diff --git a/tools/testing/selftests/kvm/include/aarch64/arch_timer.h b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > new file mode 100644 > index 000000000000..9df5b63abc47 > --- /dev/null > +++ b/tools/testing/selftests/kvm/include/aarch64/arch_timer.h > @@ -0,0 +1,142 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * ARM Generic Timer specific interface > + */ > + > +#ifndef SELFTEST_KVM_ARCH_TIMER_H > +#define SELFTEST_KVM_ARCH_TIMER_H > + > +#include "processor.h" > + > +enum arch_timer { > + VIRTUAL, > + PHYSICAL, > +}; > + > +#define CTL_ENABLE (1 << 0) > +#define CTL_IMASK (1 << 1) > +#define CTL_ISTATUS (1 << 2) > + > +#define msec_to_cycles(msec) \ > + (timer_get_cntfrq() * (uint64_t)(msec) / 1000) > + > +#define usec_to_cycles(usec) \ > + (timer_get_cntfrq() * (uint64_t)(usec) / 1000000) > + > +#define cycles_to_usec(cycles) \ > + ((uint64_t)(cycles) * 1000000 / timer_get_cntfrq()) > + > +static inline uint32_t timer_get_cntfrq(void) > +{ > + return read_sysreg(cntfrq_el0); > +} > + > +static inline uint64_t timer_get_cntct(enum arch_timer timer) > +{ > + isb(); > + > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntvct_el0); > + case PHYSICAL: > + return read_sysreg(cntpct_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_cval(enum arch_timer timer, uint64_t cval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_cval_el0, cval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_cval_el0, cval); Huh, looks like we managed to merge a backwards write_sysreg into kvm selftests. write_sysreg in the kernel and kvm-unit-tests is (value, reg). We should post a patch fixing that before adding more calls to it. > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint64_t timer_get_cval(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_cval_el0); > + case PHYSICAL: > + return read_sysreg(cntp_cval_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} > + > +static inline void timer_set_tval(enum arch_timer timer, uint32_t tval) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_tval_el0, tval); > + break; > + case PHYSICAL: > + write_sysreg(cntp_tval_el0, tval); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl) > +{ > + switch (timer) { > + case VIRTUAL: > + write_sysreg(cntv_ctl_el0, ctl); > + break; > + case PHYSICAL: > + write_sysreg(cntp_ctl_el0, ctl); > + break; > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + isb(); > +} > + > +static inline uint32_t timer_get_ctl(enum arch_timer timer) > +{ > + switch (timer) { > + case VIRTUAL: > + return read_sysreg(cntv_ctl_el0); > + case PHYSICAL: > + return read_sysreg(cntp_ctl_el0); > + default: > + GUEST_ASSERT_1(0, timer); > + } > + > + /* We should not reach here */ > + return 0; > +} I'll have to look at the test code that uses the above functions, but I wonder if it wouldn't be better to define two test functions, one for vtimer and one for ptimer where the sysreg accesses are direct, rather than all these switched wrappers. > + > +static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec) > +{ > + uint64_t now_ct = timer_get_cntct(timer); > + uint64_t next_ct = now_ct + msec_to_cycles(msec); > + > + timer_set_cval(timer, next_ct); > +} > + > +static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec) > +{ > + timer_set_tval(timer, msec_to_cycles(msec)); > +} I'll also look at how these wrappers are used, since open coding them may be OK. Thanks, drew > + > +#endif /* SELFTEST_KVM_ARCH_TIMER_H */ > -- > 2.33.0.153.gba50c8fa24-goog > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel