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(163.red-83-52-55.dynamicip.rima-tde.net. [83.52.55.163]) by smtp.gmail.com with ESMTPSA id g1sm2930192wrb.27.2021.09.02.09.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:18:12 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 23/30] target/riscv: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:36 +0200 Message-Id: <20210902161543.417092-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13575c14085..abb555a8bdb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -335,9 +335,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, env->pc = tb->pc; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -345,10 +345,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return (env->mip & env->mie) != 0; -#else - return true; -#endif } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) @@ -647,6 +645,7 @@ static const struct TCGCPUOps riscv_tcg_ops = { .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = riscv_cpu_has_work, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, @@ -666,7 +665,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; -- 2.31.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A2E4C83027 for ; Thu, 2 Sep 2021 16:37:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C602E610A0 for ; Thu, 2 Sep 2021 16:37:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C602E610A0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:52152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLpi1-0003zv-Ve for qemu-devel@archiver.kernel.org; Thu, 02 Sep 2021 12:37:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLpPz-0002Cm-TA; Thu, 02 Sep 2021 12:18:24 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43805) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mLpPw-0002gx-6C; Thu, 02 Sep 2021 12:18:23 -0400 Received: by mail-wr1-x435.google.com with SMTP id b6so3837659wrh.10; Thu, 02 Sep 2021 09:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NcTQcOUeeehYkPycaMHvSzYk1/JpDe+W3tlOioHt6ec=; b=Qo3n3nT5T2uCxZDbpwI/2fMsolvJt4Y1gOrYSxa05AyniYxnVrYAyAl58E/mePDB+Q mp74y9slo+JHNdNbb124nVsmTrRmSYtRFeXvQ45hmAzQLS7SZdoREJlqjngb5ERIDHOz 8fG18ynHtTwJKTgzScUP5EYAEGDfAkaAdwzs1bs8Mwbkci0fjxZIrzyNblhH2fEmvKn0 14gWvYc8/SbUfS0Y8MjZjc8PX2H+MElpBG7G8YmI1yDXyIqgKhSWIpr7bVwK4JmVtxvW D4kk4tzADto1QBEDwX3w/FLijcMe32GJWkC5PPc+o9liJR70fQ003gNi58OOJ6evLU1W Khjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NcTQcOUeeehYkPycaMHvSzYk1/JpDe+W3tlOioHt6ec=; b=asHlMBgp9xtbtkxENNPEl22GO7Uhtshyu6NgZMiwwl/kZiC2hSk9SXxEx4IXAXO2sH RqBn/gRgm5o98nsLpM7LZyJhkKuQ86ShrJh29DHPDZWVWTKkYBMQssmD0m/+8rNflK4o RsWsfMbW5Eba4uaFlR5op0T5hmA4OpijPiK7npCdHYxBouNLuxjlsb++UJTOH4ByUabQ 3jUuiDVahUMJeJLWgF66sL/6gXegbQu3fnUBDpDiUzas6dXdGd/hxmv47ZQGZuH8yBKR KyH842lwOVoGId/ZJRfUM1q7VG7pn925Sb37alXUuGctlLq8SnmOK4OYLNN+JTIKq+IH mIVw== X-Gm-Message-State: AOAM533GzhN++o0iqxPrk2y/UZFEjJH89R4kJNK4SUt+psdFCZXh+3i/ mYNHDtfgjQNSzx4HiNyPuj/k7+Rn9x4= X-Google-Smtp-Source: ABdhPJzq4gEgBOzEB6hIFdgS7MM2mMxbBTgou1tfWKrQyw8z4fa5k0Y3IhkCYtobsiFPzwgsy9U7mQ== X-Received: by 2002:adf:c390:: with SMTP id p16mr4949292wrf.105.1630599492959; Thu, 02 Sep 2021 09:18:12 -0700 (PDT) Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id g1sm2930192wrb.27.2021.09.02.09.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:18:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 23/30] target/riscv: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:36 +0200 Message-Id: <20210902161543.417092-24-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , kvm@vger.kernel.org, David Hildenbrand , Bin Meng , Mark Cave-Ayland , Aleksandar Rikalo , Laurent Vivier , Max Filippov , Taylor Simpson , haxm-team@intel.com, Colin Xu , "Edgar E. Iglesias" , Stafford Horne , Marek Vasut , Stefano Stabellini , Yoshinori Sato , Paul Durrant , Kamil Rytarowski , Reinoud Zandijk , Claudio Fontana , Anthony Perard , xen-devel@lists.xenproject.org, Artyom Tarasenko , Laurent Vivier , Thomas Huth , Eduardo Habkost , Richard Henderson , Greg Kurz , Cameron Esfahani , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik , Sunil Muthuswamy , Palmer Dabbelt , David Gibson , qemu-riscv@nongnu.org, Bastian Koppelmann , Chris Wulff , Roman Bolshakov , qemu-ppc@nongnu.org, Wenchao Wang , Alistair Francis , Paolo Bonzini , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13575c14085..abb555a8bdb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -335,9 +335,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, env->pc = tb->pc; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -345,10 +345,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return (env->mip & env->mie) != 0; -#else - return true; -#endif } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) @@ -647,6 +645,7 @@ static const struct TCGCPUOps riscv_tcg_ops = { .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = riscv_cpu_has_work, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, @@ -666,7 +665,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; -- 2.31.1