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Date: Thu, 2 Sep 2021 17:20:02 -0500
From: Segher Boessenkool <segher@kernel.crashing.org>
To: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [PATCH v2 1/2] powerpc/64s: system call scv tabort fix for
 corrupt irq soft-mask state
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Cc: Eirik Fuller <efuller@redhat.com>, linuxppc-dev@lists.ozlabs.org
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On Thu, Sep 02, 2021 at 04:52:03PM -0500, Segher Boessenkool wrote:
> On Thu, Sep 02, 2021 at 01:33:10PM +1000, Nicholas Piggin wrote:
> > Excerpts from Christophe Leroy's message of September 2, 2021 3:21 am:
> > >> -	/* Firstly we need to enable TM in the kernel */
> > >> +	/* We need to enable TM in the kernel, and disable EE (for scv) */
> > >>   	mfmsr	r10
> > >>   	li	r9, 1
> > >>   	rldimi	r10, r9, MSR_TM_LG, 63-MSR_TM_LG
> > >> +	LOAD_REG_IMMEDIATE(r9, MSR_EE)
> > >> +	andc	r10, r10, r9
> > > 
> > > Why not use 'rlwinm' to mask out MSR_EE ?
> > > 
> > > Something like
> > > 
> > > 	rlwinm	r10, r10, 0, ~MSR_EE
> > 
> > Mainly because I'm bad at powerpc assembly. Why do you think I'm trying 
> > to change as much as possible to C?
> 
> The actual bit (bit 31, i.e. with value 1UL << 32) cannot be cleared
> with rlwinm (only the low 32 bits can).  There are many ways to do it
> using two insns of course.

Wow I misread that, you want to clear MSR[EE] really, not MSR[TM].

You cannot use rlwinm and keep the high 32 bits of the target register
intact.  You either clear all to 0 or set them to a copy of the rotated
value in the low 32 bits.


Segher