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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v9 13/14] target/riscv: Remove RVB (replaced by Zb[abcs]
Date: Fri,  3 Sep 2021 19:00:59 +0200	[thread overview]
Message-ID: <20210903170100.2529121-14-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu>

With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.

Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
  https://lists.riscv.org/g/tech-bitmanip/message/532

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

(no changes since v3)

Changes in v3:
- Removing RVB moved into a separate commit at the tail-end of the series.

 target/riscv/cpu.c         | 26 --------------------------
 target/riscv/cpu.h         |  3 ---
 target/riscv/insn32.decode |  4 ----
 3 files changed, 33 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ceb7e01810..3a56836f1c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
     env->priv_ver = priv_ver;
 }
 
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
-    env->bext_ver = bext_ver;
-}
-
 static void set_vext_version(CPURISCVState *env, int vext_ver)
 {
     env->vext_ver = vext_ver;
@@ -496,25 +491,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
-        if (cpu->cfg.ext_b) {
-            int bext_version = BEXT_VERSION_0_93_0;
-            target_misa |= RVB;
-
-            if (cpu->cfg.bext_spec) {
-                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
-                    bext_version = BEXT_VERSION_0_93_0;
-                } else {
-                    error_setg(errp,
-                           "Unsupported bitmanip spec version '%s'",
-                           cpu->cfg.bext_spec);
-                    return;
-                }
-            } else {
-                qemu_log("bitmanip version is not specified, "
-                         "use the default value v0.93\n");
-            }
-            set_bext_version(env, bext_version);
-        }
         if (cpu->cfg.ext_v) {
             int vext_version = VEXT_VERSION_0_07_1;
             target_misa |= RVV;
@@ -586,7 +562,6 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -597,7 +572,6 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7c4cd8ea89..77e8b06106 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
-#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
@@ -83,7 +82,6 @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
-#define BEXT_VERSION_0_93_0 0x00009300
 #define VEXT_VERSION_0_07_1 0x00000701
 
 enum {
@@ -288,7 +286,6 @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
-        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index affb99b3e6..2f251dac1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -712,10 +712,6 @@ rorw       0110000 .......... 101 ..... 0111011 @r
 # instruction, so we use different handler functions to differentiate.
 zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 
-# *** RV32B Standard Extension ***
-
-# *** RV64B Standard Extension (in addition to RV32B) ***
-
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
 clmulh     0000101 .......... 011 ..... 0110011 @r
-- 
2.25.1



  parent reply	other threads:[~2021-09-03 17:15 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-03 17:00 [PATCH v9 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 02/14] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-03 18:44   ` Richard Henderson
2021-09-03 17:00 ` [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-09-03 18:45   ` Richard Henderson
2021-09-03 19:07     ` Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 04/14] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 06/14] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 08/14] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 10/14] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-03 17:00 ` [PATCH v9 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-03 17:00 ` Philipp Tomsich [this message]
2021-09-03 17:01 ` [PATCH v9 14/14] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich

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