From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B611BC433F5 for ; Sat, 4 Sep 2021 20:50:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A52160F21 for ; Sat, 4 Sep 2021 20:50:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1A52160F21 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:58106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMccs-0006wM-At for qemu-devel@archiver.kernel.org; Sat, 04 Sep 2021 16:50:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54400) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMcO0-0005yp-1n for qemu-devel@nongnu.org; Sat, 04 Sep 2021 16:35:36 -0400 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]:33699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMcNp-0002ty-Qe for qemu-devel@nongnu.org; Sat, 04 Sep 2021 16:35:32 -0400 Received: by mail-lf1-x135.google.com with SMTP id p38so5436711lfa.0 for ; Sat, 04 Sep 2021 13:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D+FLkhkHgS1RrLNfHXeZWv7czxXWrJZyGxaLuQvmLxo=; b=HosjP7Uc3jZgTBvVA59lgMRw9aNmp0tUjPzU1/uKohmHOp+ioqXk61LjcL/qiSUprr JQaxhxQTdLvcLdDstrE2hDfXYbzd2C2plk4t+wLkfoL8EKeyr/AlbnBHHjlpUApaUJGi JRcGcAlPgW1QlHUZrJ0neTUGTKV8xz91DKBiSuYIAcZy76nbs3bfL77lHi4uXGJz20DS hLA4Bkp/JOwgSHuiGxzCpGcR3jIB5tda25hqSAv6/Icv4bjoocdYABGjhXga2l8vMDzP +d8KRkkmNCS/tMC4myrWei/5sHEJEqeRCENTlf9iIVLFiY4IIqvs1er+unUC1G3q8HN2 QITw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D+FLkhkHgS1RrLNfHXeZWv7czxXWrJZyGxaLuQvmLxo=; b=b37mLw4tb42H2Ign1I6HinobrmRyxPTUdKdsTBs96pkHZtq2edga8WR/Jo8+u3nPrG CZEh5+cuc4+6oQXhirG6koxCXmrMLG8N3A/QxlI1ZoGIRF5RwmIOGA7g8nDKs2ggZiBW /9Y6t/RK5hIktAYCzUMtEHBJvHIdjDb3YOoSthEG6HvApI5sdm2Yh9xxmVvgNxY2+hTd 2E4wfd1Xs5OgQp2C+uiWWN3GnHydflUACE0K89H4AcQZFEmJPdxBFbVWIofzL5nDkw9m 9Lg5AB62fJ4I+T4qHmSKxMXympb09XtF5CxO5WS8jVtsR6s5Q+W2fligZs1ZK/faGoqg QETQ== X-Gm-Message-State: AOAM531Omh2QzGJe+SVg8YzqBAbtp7iYaeX40/mvZ7cpoQUFqXYsiu1l 0vAu6ZQpu6b3EYZNCo9UADW9/+R7oLn5JAF3J1s= X-Google-Smtp-Source: ABdhPJyR6b09yH0kvzC4tSjLEf+YWIM717Y/B1PznOQzOl/f8tqt+74wW/HDL8QQoL+UyQfZYSIRzg== X-Received: by 2002:a05:6512:3054:: with SMTP id b20mr3988694lfb.483.1630787724165; Sat, 04 Sep 2021 13:35:24 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id v15sm326304lfq.142.2021.09.04.13.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Sep 2021 13:35:23 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v10 06/16] target/riscv: Remove the W-form instructions from Zbs Date: Sat, 4 Sep 2021 22:35:05 +0200 Message-Id: <20210904203516.2570119-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> References: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x135.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form instructions for Zbs (single-bit instructions). Remove them. Note that these instructions had already been removed for the 0.93 version of the draft-B extenstion and have not been present in the binutils patches circulating in January 2021. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove the W-form instructions from Zbs in a separate commit. target/riscv/insn32.decode | 7 ---- target/riscv/insn_trans/trans_rvb.c.inc | 56 ------------------------- 2 files changed, 63 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 86f1166dab..b499691a9e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -717,10 +717,6 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -bsetw 0010100 .......... 001 ..... 0111011 @r -bclrw 0100100 .......... 001 ..... 0111011 @r -binvw 0110100 .......... 001 ..... 0111011 @r -bextw 0100100 .......... 101 ..... 0111011 @r slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r @@ -728,9 +724,6 @@ rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -bsetiw 0010100 .......... 001 ..... 0011011 @sh5 -bclriw 0100100 .......... 001 ..... 0011011 @sh5 -binviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 7f6d5aa258..ca92920efd 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -420,62 +420,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, EXT_NONE, gen_packuw); } -static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_bset); -} - -static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset); -} - -static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_bclr); -} - -static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr); -} - -static bool trans_binvw(DisasContext *ctx, arg_binvw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_binv); -} - -static bool trans_binviw(DisasContext *ctx, arg_binviw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv); -} - -static bool trans_bextw(DisasContext *ctx, arg_bextw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_bext); -} - static bool trans_slow(DisasContext *ctx, arg_slow *a) { REQUIRE_64BIT(ctx); -- 2.25.1