From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31C1BC433EF for ; Sat, 4 Sep 2021 20:41:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AACDC60C3E for ; Sat, 4 Sep 2021 20:41:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org AACDC60C3E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:37130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMcU7-00010z-OQ for qemu-devel@archiver.kernel.org; Sat, 04 Sep 2021 16:41:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMcNs-0005uc-LR for qemu-devel@nongnu.org; Sat, 04 Sep 2021 16:35:28 -0400 Received: from mail-lj1-x22a.google.com ([2a00:1450:4864:20::22a]:43758) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMcNq-0002uN-RP for qemu-devel@nongnu.org; Sat, 04 Sep 2021 16:35:28 -0400 Received: by mail-lj1-x22a.google.com with SMTP id j12so4281330ljg.10 for ; Sat, 04 Sep 2021 13:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dNAhHJK3IazavmuHWJ2dYAB2ul4aGgSASJVaHSi/TkM=; b=eJVmCXw0YN4diMxI8sC5SbHejLSCY/HZBPsaXcA+LpLNwnSsWGufVo6hcyXGDJ7FAg jMeMug6SKw97LSG76pGFl39Ikl7pO0Kxz28XgtDZDcnxEIwoYLbwUSz+IiUkN4Icf8CK oTaS+yQCaVcI97qRhQxGftfr1DE4w6ajSoUW8VLqrFh3QhjZoMK9SJ1UUAjtc9uapQBB rWKXOsT1144WqeY/Mb5Lg6gGtyyB2kwDQTq1fgc113Gz53wm05RfnhtSJ77N884a9+WC jV9kJTH+2yMC+MMxsCyRGZduFTs0fGAiZP6wVz/uYwk8LOl4C8vgeO6XQAcPrWnJthk3 nOGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dNAhHJK3IazavmuHWJ2dYAB2ul4aGgSASJVaHSi/TkM=; b=nV8plgkfgievMeMwWFd6ew7ylnZL8jgXivdrIa1G6Bnz4192+OHPlGIVqu5agkleCG nzeXkm02uvCjTTdX5xx+3S0mkjTzwGD4UiGhHhhU/KSr+kY1ySrWXI/Ccnojea9PSxeG Z9aEiWcklLNH0pUErP1RK67MD8YC/VpyBjmV3wlV5/tkWB0+sRnpAWV/Po/BhAaAxZVK Gir3wJ76L3/CgMG2WdLjbQm6KXynvS/S4YWbvbvW8ZQLVXBB9inJDg6IgXHPD1c8L7QP 9QABIUc69aMdKvsL0zMqlkAUEJDzi7KeUqJWhkkpb/GKwdEK8RuSExqQw+ii7PUgdNHk Pxzw== X-Gm-Message-State: AOAM532fxw45QaJP0+q/dqyfPA9T/PkfAa2xCxexy4KNWbtJImZUWqC+ OK7g2yhtqiqqAHg8YqGBk2brjrp3HZcvKrWzLKI= X-Google-Smtp-Source: ABdhPJyXImGykL6E13B1vbhZ6hVFaViD+3hk+9iiSC0OMb87bsKxTeFF14fWIJKDuQmAtLXpfb3vXw== X-Received: by 2002:a2e:8e39:: with SMTP id r25mr4005743ljk.272.1630787724872; Sat, 04 Sep 2021 13:35:24 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id v15sm326304lfq.142.2021.09.04.13.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Sep 2021 13:35:24 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v10 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Date: Sat, 4 Sep 2021 22:35:06 +0200 Message-Id: <20210904203516.2570119-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> References: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove shift-one instructions in a separate commit. target/riscv/insn32.decode | 8 --- target/riscv/insn_trans/trans_rvb.c.inc | 70 ------------------------- 2 files changed, 78 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b499691a9e..e0f6e315a2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -693,8 +693,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -704,8 +702,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -717,15 +713,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index ca92920efd..9891c4912a 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -420,38 +382,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, EXT_NONE, gen_packuw); } -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32(); -- 2.25.1