From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5103C4332F for ; Sun, 5 Sep 2021 14:27:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A735560F21 for ; Sun, 5 Sep 2021 14:27:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233673AbhIEO2l (ORCPT ); Sun, 5 Sep 2021 10:28:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:51728 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbhIEO2k (ORCPT ); Sun, 5 Sep 2021 10:28:40 -0400 Received: from jic23-huawei (cpc108967-cmbg20-2-0-cust86.5-4.cable.virginm.net [81.101.6.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 1C6C760F3A; Sun, 5 Sep 2021 14:27:31 +0000 (UTC) Date: Sun, 5 Sep 2021 15:30:54 +0100 From: Jonathan Cameron To: Billy Tsai Cc: , , , , , , , , , , , , , Subject: Re: [v5 03/15] iio: adc: aspeed: completes the bitfield declare. Message-ID: <20210905153054.56159999@jic23-huawei> In-Reply-To: <20210831071458.2334-4-billy_tsai@aspeedtech.com> References: <20210831071458.2334-1-billy_tsai@aspeedtech.com> <20210831071458.2334-4-billy_tsai@aspeedtech.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 31 Aug 2021 15:14:46 +0800 Billy Tsai wrote: > This patch completes the declare of ADC register bitfields and uses the > same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space > alignment of the codes. > > Signed-off-by: Billy Tsai LGTM Applied to the togreg branch of iio.git. Note this won't be going out as non rebasing for a while yet (given mid merge window) so if anyone else has time to look at this that would be much appreciated! Jonathan > --- > drivers/iio/adc/aspeed_adc.c | 64 ++++++++++++++++++++++++++---------- > 1 file changed, 47 insertions(+), 17 deletions(-) > > diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c > index 34ec0c28b2df..f055fe7b2c40 100644 > --- a/drivers/iio/adc/aspeed_adc.c > +++ b/drivers/iio/adc/aspeed_adc.c > @@ -3,6 +3,7 @@ > * Aspeed AST2400/2500 ADC > * > * Copyright (C) 2017 Google, Inc. > + * Copyright (C) 2021 Aspeed Technology Inc. > */ > > #include > @@ -16,6 +17,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,15 +30,39 @@ > #define ASPEED_REG_INTERRUPT_CONTROL 0x04 > #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 > #define ASPEED_REG_CLOCK_CONTROL 0x0C > -#define ASPEED_REG_MAX 0xC0 > - > -#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) > -#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) > -#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) > - > -#define ASPEED_ENGINE_ENABLE BIT(0) > - > -#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_REG_COMPENSATION_TRIM 0xC4 > +/* > + * The register offset between 0xC8~0xCC can be read and won't affect the > + * hardware logic in each version of ADC. > + */ > +#define ASPEED_REG_MAX 0xD0 > + > +#define ASPEED_ADC_ENGINE_ENABLE BIT(0) > +#define ASPEED_ADC_OP_MODE GENMASK(3, 1) > +#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 > +#define ASPEED_ADC_OP_MODE_STANDBY 1 > +#define ASPEED_ADC_OP_MODE_NORMAL 7 > +#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) > +#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) > +/* > + * Bit 6 determines not only the reference voltage range but also the dividing > + * circuit for battery sensing. > + */ > +#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) > +#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 > +#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 > +#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) > +#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 > +#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 > +#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_ADC_CH7_MODE BIT(12) > +#define ASPEED_ADC_CH7_NORMAL 0 > +#define ASPEED_ADC_CH7_BAT 1 > +#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) > +#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) > +#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) > > #define ASPEED_ADC_INIT_POLLING_TIME 500 > #define ASPEED_ADC_INIT_TIMEOUT 500000 > @@ -227,7 +253,9 @@ static int aspeed_adc_probe(struct platform_device *pdev) > > if (model_data->wait_init_sequence) { > /* Enable engine in normal mode. */ > - writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, > + ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE, > data->base + ASPEED_REG_ENGINE_CONTROL); > > /* Wait for initial sequence complete. */ > @@ -246,10 +274,12 @@ static int aspeed_adc_probe(struct platform_device *pdev) > if (ret) > goto clk_enable_error; > > - adc_engine_control_reg_val = GENMASK(31, 16) | > - ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; > + adc_engine_control_reg_val = > + ASPEED_ADC_CTRL_CHANNEL | > + FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE; > writel(adc_engine_control_reg_val, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + data->base + ASPEED_REG_ENGINE_CONTROL); > > model_data = of_device_get_match_data(&pdev->dev); > indio_dev->name = model_data->model_name; > @@ -265,8 +295,8 @@ static int aspeed_adc_probe(struct platform_device *pdev) > return 0; > > iio_register_error: > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > clk_enable_error: > poll_timeout_error: > @@ -284,8 +314,8 @@ static int aspeed_adc_remove(struct platform_device *pdev) > struct aspeed_adc_data *data = iio_priv(indio_dev); > > iio_device_unregister(indio_dev); > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > reset_control_assert(data->rst); > clk_hw_unregister_divider(data->clk_scaler); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1062DC433EF for ; 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Sun, 5 Sep 2021 14:27:31 +0000 (UTC) Date: Sun, 5 Sep 2021 15:30:54 +0100 From: Jonathan Cameron To: Billy Tsai Cc: , , , , , , , , , , , , , Subject: Re: [v5 03/15] iio: adc: aspeed: completes the bitfield declare. Message-ID: <20210905153054.56159999@jic23-huawei> In-Reply-To: <20210831071458.2334-4-billy_tsai@aspeedtech.com> References: <20210831071458.2334-1-billy_tsai@aspeedtech.com> <20210831071458.2334-4-billy_tsai@aspeedtech.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210905_072737_476656_16555B09 X-CRM114-Status: GOOD ( 25.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 31 Aug 2021 15:14:46 +0800 Billy Tsai wrote: > This patch completes the declare of ADC register bitfields and uses the > same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space > alignment of the codes. > > Signed-off-by: Billy Tsai LGTM Applied to the togreg branch of iio.git. Note this won't be going out as non rebasing for a while yet (given mid merge window) so if anyone else has time to look at this that would be much appreciated! Jonathan > --- > drivers/iio/adc/aspeed_adc.c | 64 ++++++++++++++++++++++++++---------- > 1 file changed, 47 insertions(+), 17 deletions(-) > > diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c > index 34ec0c28b2df..f055fe7b2c40 100644 > --- a/drivers/iio/adc/aspeed_adc.c > +++ b/drivers/iio/adc/aspeed_adc.c > @@ -3,6 +3,7 @@ > * Aspeed AST2400/2500 ADC > * > * Copyright (C) 2017 Google, Inc. > + * Copyright (C) 2021 Aspeed Technology Inc. > */ > > #include > @@ -16,6 +17,7 @@ > #include > #include > #include > +#include > > #include > #include > @@ -28,15 +30,39 @@ > #define ASPEED_REG_INTERRUPT_CONTROL 0x04 > #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 > #define ASPEED_REG_CLOCK_CONTROL 0x0C > -#define ASPEED_REG_MAX 0xC0 > - > -#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1) > -#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1) > -#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1) > - > -#define ASPEED_ENGINE_ENABLE BIT(0) > - > -#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_REG_COMPENSATION_TRIM 0xC4 > +/* > + * The register offset between 0xC8~0xCC can be read and won't affect the > + * hardware logic in each version of ADC. > + */ > +#define ASPEED_REG_MAX 0xD0 > + > +#define ASPEED_ADC_ENGINE_ENABLE BIT(0) > +#define ASPEED_ADC_OP_MODE GENMASK(3, 1) > +#define ASPEED_ADC_OP_MODE_PWR_DOWN 0 > +#define ASPEED_ADC_OP_MODE_STANDBY 1 > +#define ASPEED_ADC_OP_MODE_NORMAL 7 > +#define ASPEED_ADC_CTRL_COMPENSATION BIT(4) > +#define ASPEED_ADC_AUTO_COMPENSATION BIT(5) > +/* > + * Bit 6 determines not only the reference voltage range but also the dividing > + * circuit for battery sensing. > + */ > +#define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) > +#define ASPEED_ADC_REF_VOLTAGE_2500mV 0 > +#define ASPEED_ADC_REF_VOLTAGE_1200mV 1 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 > +#define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 > +#define ASPEED_ADC_BAT_SENSING_DIV BIT(6) > +#define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 > +#define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 > +#define ASPEED_ADC_CTRL_INIT_RDY BIT(8) > +#define ASPEED_ADC_CH7_MODE BIT(12) > +#define ASPEED_ADC_CH7_NORMAL 0 > +#define ASPEED_ADC_CH7_BAT 1 > +#define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) > +#define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) > +#define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) > > #define ASPEED_ADC_INIT_POLLING_TIME 500 > #define ASPEED_ADC_INIT_TIMEOUT 500000 > @@ -227,7 +253,9 @@ static int aspeed_adc_probe(struct platform_device *pdev) > > if (model_data->wait_init_sequence) { > /* Enable engine in normal mode. */ > - writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE, > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, > + ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE, > data->base + ASPEED_REG_ENGINE_CONTROL); > > /* Wait for initial sequence complete. */ > @@ -246,10 +274,12 @@ static int aspeed_adc_probe(struct platform_device *pdev) > if (ret) > goto clk_enable_error; > > - adc_engine_control_reg_val = GENMASK(31, 16) | > - ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; > + adc_engine_control_reg_val = > + ASPEED_ADC_CTRL_CHANNEL | > + FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | > + ASPEED_ADC_ENGINE_ENABLE; > writel(adc_engine_control_reg_val, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + data->base + ASPEED_REG_ENGINE_CONTROL); > > model_data = of_device_get_match_data(&pdev->dev); > indio_dev->name = model_data->model_name; > @@ -265,8 +295,8 @@ static int aspeed_adc_probe(struct platform_device *pdev) > return 0; > > iio_register_error: > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > clk_enable_error: > poll_timeout_error: > @@ -284,8 +314,8 @@ static int aspeed_adc_remove(struct platform_device *pdev) > struct aspeed_adc_data *data = iio_priv(indio_dev); > > iio_device_unregister(indio_dev); > - writel(ASPEED_OPERATION_MODE_POWER_DOWN, > - data->base + ASPEED_REG_ENGINE_CONTROL); > + writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), > + data->base + ASPEED_REG_ENGINE_CONTROL); > clk_disable_unprepare(data->clk_scaler->clk); > reset_control_assert(data->rst); > clk_hw_unregister_divider(data->clk_scaler); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel