From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEF97C433F5 for ; Mon, 6 Sep 2021 02:15:51 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 59265604AC for ; Mon, 6 Sep 2021 02:15:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 59265604AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C402E410F0; Mon, 6 Sep 2021 04:15:50 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id C3AC140E5A for ; Mon, 6 Sep 2021 04:15:48 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10098"; a="206978782" X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="206978782" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2021 19:15:47 -0700 X-IronPort-AV: E=Sophos;i="5.85,271,1624345200"; d="scan'208";a="536351032" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2021 19:15:43 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, helin.zhang@intel.com, jingjing.wu@intel.com, remy.horton@intel.com, jijiang.liu@intel.com, jing.d.chen@intel.com, heqing.zhu@intel.com, cunming.liang@intel.com, wenzhuo.lu@intel.com, roy.fan.zhang@intel.com, andrey.chilikin@intel.com, echaudro@redhat.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , Stanislaw Grzeszczak Date: Mon, 6 Sep 2021 02:02:42 +0000 Message-Id: <20210906020258.1291688-3-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210906020258.1291688-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> <20210906020258.1291688-1-robinx.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4 02/18] net/i40e/base: add support for Min Rollback Revision for 4 more X722 modules X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This change increments X722 API version and adds new constants related to the extended implementation of Security Version Opt-In. Signed-off-by: Stanislaw Grzeszczak Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 2ca41db5d3..a96527f31c 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -12,7 +12,7 @@ */ #define I40E_FW_API_VERSION_MAJOR 0x0001 -#define I40E_FW_API_VERSION_MINOR_X722 0x000B +#define I40E_FW_API_VERSION_MINOR_X722 0x000C #define I40E_FW_API_VERSION_MINOR_X710 0x000C #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ @@ -2425,11 +2425,15 @@ struct i40e_aqc_rollback_revision_update { u8 optin_mode; /* bool */ #define I40E_AQ_RREV_OPTION_MODE 0x01 u8 module_selected; -#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 -#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 -#define I40E_AQ_RREV_MODULE_OPTION_ROM 2 -#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 -#define I40E_AQ_RREV_MODULE_PE_IMAGE 4 +#define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0 +#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1 +#define I40E_AQ_RREV_MODULE_OPTION_ROM 2 +#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3 +#define I40E_AQ_RREV_MODULE_PE_IMAGE 4 +#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION 5 +#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION 6 +#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION 7 +#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION 8 u8 reserved1[2]; u32 min_rrev; u8 reserved2[8]; -- 2.25.1