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Mon, 6 Sep 2021 03:44:18 +0000 (UTC) From: Dave Airlie To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@linux.intel.com, Dave Airlie Date: Mon, 6 Sep 2021 13:43:53 +1000 Message-Id: <20210906034356.2946530-8-airlied@gmail.com> In-Reply-To: <20210906034356.2946530-1-airlied@gmail.com> References: <20210906034356.2946530-1-airlied@gmail.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: gmail.com Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="US-ASCII" Subject: [Intel-gfx] [PATCH 07/10] drm/i915/display: move pps_mmio_base to display struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dave Airlie Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_pps.c | 6 +++--- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i91= 5/display/intel_pps.c index a36ec4a818ff..857f3da80e26 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1402,9 +1402,9 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private= *dev_priv) void intel_pps_setup(struct drm_i915_private *i915) { =09if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) -=09=09i915->pps_mmio_base =3D PCH_PPS_BASE; +=09=09i915->display.pps_mmio_base =3D PCH_PPS_BASE; =09else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) -=09=09i915->pps_mmio_base =3D VLV_PPS_BASE; +=09=09i915->display.pps_mmio_base =3D VLV_PPS_BASE; =09else -=09=09i915->pps_mmio_base =3D PPS_BASE; +=09=09i915->display.pps_mmio_base =3D PPS_BASE; } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index 2d4cac666de9..4194a2042abf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -857,6 +857,8 @@ struct drm_i915_display { =09/* MMIO base address for MIPI regs */ =09u32 mipi_mmio_base; =20 +=09u32 pps_mmio_base; + =09struct intel_gmbus gmbus[GMBUS_NUM_PINS]; =20 =09/** gmbus_mutex protects against concurrent usage of the single hw gmbu= s @@ -915,8 +917,6 @@ struct drm_i915_private { =20 =09struct intel_wopcm wopcm; =20 -=09u32 pps_mmio_base; - =09struct pci_dev *bridge_dev; =20 =09struct rb_root uabi_engines; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index 948949c15396..7afb6aa554c0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5166,7 +5166,7 @@ enum { #define VLV_PPS_BASE=09=09=09(VLV_DISPLAY_BASE + PPS_BASE) #define PCH_PPS_BASE=09=09=090xC7200 =20 -#define _MMIO_PPS(pps_idx, reg)=09=09_MMIO(dev_priv->pps_mmio_base -=09\ +#define _MMIO_PPS(pps_idx, reg)=09=09_MMIO(dev_priv->display.pps_mmio_base= -=09\ =09=09=09=09=09 PPS_BASE + (reg) +=09\ =09=09=09=09=09 (pps_idx) * 0x100) =20 --=20 2.31.1