All of lore.kernel.org
 help / color / mirror / Atom feed
From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Lara Lazier <laramglazier@gmail.com>
Subject: [PULL 06/36] target/i386: Added changed priority check for VIRQ
Date: Mon,  6 Sep 2021 15:10:29 +0200	[thread overview]
Message-ID: <20210906131059.55234-7-pbonzini@redhat.com> (raw)
In-Reply-To: <20210906131059.55234-1-pbonzini@redhat.com>

From: Lara Lazier <laramglazier@gmail.com>

Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.h                    | 15 +++++++++++++++
 target/i386/tcg/sysemu/misc_helper.c |  7 +++++++
 target/i386/tcg/sysemu/svm_helper.c  | 15 ---------------
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d26df6de6b..69e722253d 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2245,6 +2245,21 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env)
     return reserved_bits;
 }
 
+static inline bool ctl_has_irq(CPUX86State *env)
+{
+    uint32_t int_prio;
+    uint32_t tpr;
+
+    int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
+    tpr = env->int_ctl & V_TPR_MASK;
+
+    if (env->int_ctl & V_IGN_TPR_MASK) {
+        return (env->int_ctl & V_IRQ_MASK);
+    }
+
+    return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
+}
+
 #if defined(TARGET_X86_64) && \
     defined(CONFIG_USER_ONLY) && \
     defined(CONFIG_LINUX)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 91b0fc916b..9ccaa054c4 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -122,6 +122,13 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
             qemu_mutex_unlock_iothread();
         }
         env->int_ctl = (env->int_ctl & ~V_TPR_MASK) | (t0 & V_TPR_MASK);
+
+        CPUState *cs = env_cpu(env);
+        if (ctl_has_irq(env)) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
+        }
         break;
     default:
         env->cr[reg] = t0;
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index a35b79548a..7bbd3a18c9 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -76,21 +76,6 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
                            sc->base, sc->limit, sc->flags);
 }
 
-static inline bool ctl_has_irq(CPUX86State *env)
-{
-    uint32_t int_prio;
-    uint32_t tpr;
-
-    int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
-    tpr = env->int_ctl & V_TPR_MASK;
-
-    if (env->int_ctl & V_IGN_TPR_MASK) {
-        return env->int_ctl & V_IRQ_MASK;
-    }
-
-    return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
-}
-
 static inline bool is_efer_invalid_state (CPUX86State *env)
 {
     if (!(env->efer & MSR_EFER_SVME)) {
-- 
2.31.1




  parent reply	other threads:[~2021-09-06 13:19 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-06 13:10 [PULL 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-06 13:10 ` [PULL 01/36] target/i386: VMRUN and VMLOAD canonicalizations Paolo Bonzini
2021-09-06 13:10 ` [PULL 02/36] target/i386: Added VGIF feature Paolo Bonzini
2021-09-06 13:10 ` [PULL 03/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini
2021-09-06 13:10 ` [PULL 04/36] target/i386: Added VGIF V_IRQ masking capability Paolo Bonzini
2021-09-06 13:10 ` [PULL 05/36] target/i386: Added ignore TPR check in ctl_has_irq Paolo Bonzini
2021-09-06 13:10 ` Paolo Bonzini [this message]
2021-09-06 13:10 ` [PULL 07/36] target/i386: Added vVMLOAD and vVMSAVE feature Paolo Bonzini
2021-09-06 13:10 ` [PULL 08/36] configure / meson: Move the GBM handling to meson.build Paolo Bonzini
2021-09-06 13:26   ` Thomas Huth
2021-09-06 13:10 ` [PULL 09/36] memory: Add RAM_PROTECTED flag to skip IOMMU mappings Paolo Bonzini
2021-09-06 13:10 ` [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC Paolo Bonzini
2021-09-07  6:23   ` Yang Zhong
2021-09-06 13:10 ` [PULL 11/36] qom: Add memory-backend-epc ObjectOptions support Paolo Bonzini
2021-09-06 13:10 ` [PULL 12/36] i386: Add 'sgx-epc' device to expose EPC sections to guest Paolo Bonzini
2021-09-06 13:10 ` [PULL 13/36] vl: Add sgx compound properties to expose SGX " Paolo Bonzini
2021-09-06 13:10 ` [PULL 14/36] i386: Add primary SGX CPUID and MSR defines Paolo Bonzini
2021-09-06 13:10 ` [PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX Paolo Bonzini
2021-09-06 13:10 ` [PULL 16/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX Paolo Bonzini
2021-09-06 13:10 ` [PULL 17/36] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX Paolo Bonzini
2021-09-06 13:10 ` [PULL 18/36] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs Paolo Bonzini
2021-09-06 13:10 ` [PULL 19/36] i386: Add feature control MSR dependency when SGX is enabled Paolo Bonzini
2021-09-06 13:10 ` [PULL 20/36] i386: Update SGX CPUID info according to hardware/KVM/user input Paolo Bonzini
2021-09-06 13:10 ` [PULL 21/36] i386: kvm: Add support for exposing PROVISIONKEY to guest Paolo Bonzini
2021-09-06 13:10 ` [PULL 22/36] i386: Propagate SGX CPUID sub-leafs to KVM Paolo Bonzini
2021-09-06 13:10 ` [PULL 23/36] Adjust min CPUID level to 0x12 when SGX is enabled Paolo Bonzini
2021-09-06 13:10 ` [PULL 24/36] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Paolo Bonzini
2021-09-06 13:10 ` [PULL 25/36] hw/i386/pc: Account for SGX EPC sections when calculating device memory Paolo Bonzini
2021-09-06 13:10 ` [PULL 26/36] i386/pc: Add e820 entry for SGX EPC section(s) Paolo Bonzini
2021-09-06 13:10 ` [PULL 27/36] i386: acpi: Add SGX EPC entry to ACPI tables Paolo Bonzini
2021-09-06 13:10 ` [PULL 28/36] q35: Add support for SGX EPC Paolo Bonzini
2021-09-06 13:10 ` [PULL 29/36] i440fx: " Paolo Bonzini
2021-09-06 13:10 ` [PULL 30/36] hostmem-epc: Add the reset interface for EPC backend reset Paolo Bonzini
2021-09-06 13:10 ` [PULL 31/36] sgx-epc: Add the reset interface for sgx-epc virt device Paolo Bonzini
2021-09-06 13:10 ` [PULL 32/36] sgx-epc: Avoid bios reset during sgx epc initialization Paolo Bonzini
2021-09-06 13:10 ` [PULL 33/36] hostmem-epc: Make prealloc consistent with qemu cmdline during reset Paolo Bonzini
2021-09-06 13:10 ` [PULL 34/36] Kconfig: Add CONFIG_SGX support Paolo Bonzini
2021-09-06 13:10 ` [PULL 35/36] sgx-epc: Add the fill_device_info() callback support Paolo Bonzini
2021-09-06 13:10 ` [PULL 36/36] doc: Add the SGX doc Paolo Bonzini
2021-09-06 14:03 ` [PULL 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210906131059.55234-7-pbonzini@redhat.com \
    --to=pbonzini@redhat.com \
    --cc=laramglazier@gmail.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.