From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7F0FC433F5 for ; Tue, 7 Sep 2021 08:39:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD4EB6105A for ; Tue, 7 Sep 2021 08:39:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243081AbhIGIk5 (ORCPT ); Tue, 7 Sep 2021 04:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242989AbhIGIkq (ORCPT ); Tue, 7 Sep 2021 04:40:46 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63F78C0613CF for ; Tue, 7 Sep 2021 01:39:40 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id n5so13201080wro.12 for ; Tue, 07 Sep 2021 01:39:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tmdXYabHBlH0lzTR2aGEg4jjkPTidI1mG07cS/MQyTc=; b=b3dS4AUF3x8YJP0MHj9VQNJzu+5FaEBv2n1zRCv3YXmTXTkGkm+SQIVEeNELn0Ckbi S6aAexEhIXCCSetvenP4sRLVOQiZZPluj+9Tojdmc/XdQPToUkLX+WhtHtZqAsVToK9R PKS1wKnI7TIigejl8kDKT2AWgebp9s5WaMQTkWEHQRfGdtdh4UcGYFD4jHuJ1p71coHa El4whTjb3Qj8bHoRpMKmQp7CWpUgqYCHlI+wSwN/zANsgburryHCFv55vYf0q0eEqDjp rl/pSLdm4qvpRm9QMmkWJvbHVa00DnEaeRUnLyeeARI7qWzXs+uKnJIZxrxC9dxXW99j qnTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tmdXYabHBlH0lzTR2aGEg4jjkPTidI1mG07cS/MQyTc=; b=QktrtdcfQGw041ugA8O5Eh5ZgjSxDDkAZoPO2uSxoiHiyV0s85SUV/0L+/TFOu3B5L 5fBsfahUwc146cxWOIa7MvFJpEhHdiKMivjr5Q5i6b3Wc60m+efsiG8ihbk4ri/YB2Or 4LIrbJNz1rqeI/eJT6oAQlwZTXZnxxd4e/bq2XNGSSKxnYSQwC9mBH3YI9KhhiBy9KAs EN1OwB2Km2/Z+aMvSjkl+5G2xTV9Lvv6X781BY7OxY796ldl1+J75/3r/FeRsUQemF05 QSUJz8FdKIzAyBNNmDnBjkWj3RSviniCr/5txV4btPZ5M5kbU0qh+5QB1FoDE/bFBZF3 kEWg== X-Gm-Message-State: AOAM532wOQ3wgAAwOg+8VfRTdEaGxCdqefbOzUULlNWTYUXZeiaDz8WG rmxxkErKIDARWqGsYsnj9ZH04Q== X-Google-Smtp-Source: ABdhPJyDgiMvPKHxYxRk/TRfiki81RSVnZoaBVGMlrlfdZYclA0TZPFkDpfqZUikhceozNhYswoUCA== X-Received: by 2002:adf:9e4d:: with SMTP id v13mr17418975wre.26.1631003979019; Tue, 07 Sep 2021 01:39:39 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-3317-3074-96af-9642-0002.rev.sfr.net. [2a02:8440:6141:3317:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id m186sm1737027wme.48.2021.09.07.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 01:39:38 -0700 (PDT) From: Guillaume Ranquet Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Tue, 7 Sep 2021 10:37:21 +0200 Message-Id: <20210907083723.7725-5-granquet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907083723.7725-1-granquet@baylibre.com> References: <20210907083723.7725-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..ae3cc0ae457f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..b5d5f7f79c71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: HDMI clock for vpp_split module + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>, + <&topckgen CLK_TOP_MSDCPLL_D2>, + <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_UNIVPLL_D4_D8>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +... -- 2.31.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E2AFC433FE for ; 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[2a02:8440:6141:3317:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id m186sm1737027wme.48.2021.09.07.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 01:39:38 -0700 (PDT) From: Guillaume Ranquet To: Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Tue, 7 Sep 2021 10:37:21 +0200 Message-Id: <20210907083723.7725-5-granquet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907083723.7725-1-granquet@baylibre.com> References: <20210907083723.7725-1-granquet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210907_013940_331938_5772EC85 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..ae3cc0ae457f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..b5d5f7f79c71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: HDMI clock for vpp_split module + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>, + <&topckgen CLK_TOP_MSDCPLL_D2>, + <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_UNIVPLL_D4_D8>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +... -- 2.31.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98302C433EF for ; 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[2a02:8440:6141:3317:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id m186sm1737027wme.48.2021.09.07.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 01:39:38 -0700 (PDT) From: Guillaume Ranquet To: Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Tue, 7 Sep 2021 10:37:21 +0200 Message-Id: <20210907083723.7725-5-granquet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907083723.7725-1-granquet@baylibre.com> References: <20210907083723.7725-1-granquet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210907_013940_375625_90E04B33 X-CRM114-Status: GOOD ( 15.09 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..ae3cc0ae457f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..b5d5f7f79c71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: HDMI clock for vpp_split module + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>, + <&topckgen CLK_TOP_MSDCPLL_D2>, + <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_UNIVPLL_D4_D8>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +... -- 2.31.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EB8AC433EF for ; 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[2a02:8440:6141:3317:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id m186sm1737027wme.48.2021.09.07.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 01:39:38 -0700 (PDT) From: Guillaume Ranquet To: Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Tue, 7 Sep 2021 10:37:21 +0200 Message-Id: <20210907083723.7725-5-granquet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907083723.7725-1-granquet@baylibre.com> References: <20210907083723.7725-1-granquet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210907_013940_349074_6A68C3B5 X-CRM114-Status: GOOD ( 16.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..ae3cc0ae457f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..b5d5f7f79c71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: HDMI clock for vpp_split module + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>, + <&topckgen CLK_TOP_MSDCPLL_D2>, + <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_UNIVPLL_D4_D8>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +... -- 2.31.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51058C433FE for ; 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[2a02:8440:6141:3317:3074:96af:9642:2]) by smtp.gmail.com with ESMTPSA id m186sm1737027wme.48.2021.09.07.01.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 01:39:38 -0700 (PDT) From: Guillaume Ranquet To: Cc: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , CK Hu , Jitao shi , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings Date: Tue, 7 Sep 2021 10:37:21 +0200 Message-Id: <20210907083723.7725-5-granquet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210907083723.7725-1-granquet@baylibre.com> References: <20210907083723.7725-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 07 Sep 2021 10:28:27 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC. Signed-off-by: Guillaume Ranquet --- .../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++ .../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml new file mode 100644 index 000000000000..ae3cc0ae457f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi-ddc + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ddc-i2c + +required: + - compatible + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; + }; + +... diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml new file mode 100644 index 000000000000..b5d5f7f79c71 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek HDMI Encoder Device Tree Bindings for mt8195 + +maintainers: + - CK Hu + - Jitao shi + +description: | + The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from + its parallel input. + +properties: + compatible: + enum: + - mediatek,mt8195-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PLL divider + - description: PLL divider + - description: HDCP engine clock + - description: PLL divider + - description: HDCP engine clock + - description: Bus clock + - description: HDMI clock for vpp_split module + + clock-names: + items: + - const: univpll_d6_d4 + - const: msdcpll_d2 + - const: hdmi_apb_sel + - const: univpll_d4_d8 + - const: hdcp_sel + - const: hdcp24_sel + - const: split_hdmi + + phys: + maxItems: 1 + + phy-names: + items: + - const: hdmi + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>, + <&topckgen CLK_TOP_MSDCPLL_D2>, + <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_UNIVPLL_D4_D8>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "univpll_d6_d4", + "msdcpll_d2", + "hdmi_apb_sel", + "univpll_d4_d8", + "hdcp_sel", + "hdcp24_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + +... -- 2.31.1