From: Animesh Manna <animesh.manna@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: gwan-gyeong.mun@intel.com, mika.kahola@intel.com,
jani.nikula@intel.com, manasi.d.navare@intel.com,
Animesh Manna <animesh.manna@intel.com>
Subject: [Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable panel replay
Date: Wed, 8 Sep 2021 14:45:43 +0530 [thread overview]
Message-ID: <20210908091544.13772-5-animesh.manna@intel.com> (raw)
In-Reply-To: <20210908091544.13772-1-animesh.manna@intel.com>
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_dp_helper.h | 3 +++
3 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 660e19c10aa8..1dc6b340d745 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -369,8 +369,12 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.pr_enabled) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+ PANEL_REPLAY_ENABLE);
+ return;
+ } else if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -497,6 +501,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
return val;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+ ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+ TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1077,8 +1092,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ /* psr1, psr2 and panel-replay are mutually exclusive.*/
+ if (intel_dp->psr.pr_enabled)
+ dg2_activate_panel_replay(intel_dp);
+ else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1267,7 +1284,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.pr_enabled) {
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+ TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+ } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_read(dev_priv,
EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bc8f22fa9a8..9effbc6e5539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4720,6 +4720,7 @@ enum {
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1b4dcee3b281..63face4e4f6f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -707,6 +707,9 @@ struct drm_panel;
#define DP_BRANCH_DEVICE_CTRL 0x1a1
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0
+# define PANEL_REPLAY_ENABLE (1 << 0)
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
--
2.29.0
next prev parent reply other threads:[~2021-09-08 9:38 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 9:15 [Intel-gfx] [RFC 0/5] Panel replay phase1 implementation Animesh Manna
2021-09-08 9:15 ` [Intel-gfx] [RFC 1/5] drm/i915/panelreplay: update plane selective fetch register definition Animesh Manna
2021-09-08 19:26 ` Souza, Jose
2021-09-08 19:39 ` Manna, Animesh
2021-09-08 9:15 ` [Intel-gfx] [RFC 2/5] drm/i915/panelreplay: Feature flag added for panel replay Animesh Manna
2021-09-08 19:29 ` Souza, Jose
2021-09-08 9:15 ` [Intel-gfx] [RFC 3/5] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
2021-09-08 12:52 ` kernel test robot
2021-09-08 12:52 ` kernel test robot
2021-09-08 14:07 ` kernel test robot
2021-09-08 14:07 ` kernel test robot
2021-09-08 19:31 ` Souza, Jose
2021-09-08 19:50 ` Manna, Animesh
2021-09-08 19:55 ` Souza, Jose
2021-09-08 9:15 ` Animesh Manna [this message]
2021-09-08 19:41 ` [Intel-gfx] [RFC 4/5] drm/i915/panelreplay: enable/disable " Souza, Jose
2021-09-08 9:15 ` [Intel-gfx] [RFC 5/5] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
2021-09-08 10:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation Patchwork
2021-09-08 10:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-08 11:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-08 14:19 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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