From: Swapnil Jakhade <sjakhade@cadence.com> To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>, <p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>, <a-govindraju@ti.com> Subject: [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Date: Wed, 8 Sep 2021 14:29:15 +0200 [thread overview] Message-ID: <20210908122930.10224-1-sjakhade@cadence.com> (raw) Cadence Sierra PHY is a multiprotocol PHY supporting different multilink PHY configurations. This patch series extends functionality of Sierra PHY driver by adding features like support for multilink multiprotocol configurations, derived reference clock etc. The changes have been validated on TI J721E platform. Version History: v2: - Added a new patch 3/15 to rename the SSC macros for dt-bindings to use generic names. These macros are not yet used in any DTS file. Swapnil Jakhade (15): phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add support for derived reference clock output .../bindings/phy/phy-cadence-sierra.yaml | 9 + .../bindings/phy/phy-cadence-torrent.yaml | 4 +- drivers/phy/cadence/phy-cadence-sierra.c | 1299 +++++++++++++++-- include/dt-bindings/phy/phy-cadence.h | 9 +- 4 files changed, 1226 insertions(+), 95 deletions(-) -- 2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Swapnil Jakhade <sjakhade@cadence.com> To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>, <p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>, <a-govindraju@ti.com> Subject: [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Date: Wed, 8 Sep 2021 14:29:15 +0200 [thread overview] Message-ID: <20210908122930.10224-1-sjakhade@cadence.com> (raw) Cadence Sierra PHY is a multiprotocol PHY supporting different multilink PHY configurations. This patch series extends functionality of Sierra PHY driver by adding features like support for multilink multiprotocol configurations, derived reference clock etc. The changes have been validated on TI J721E platform. Version History: v2: - Added a new patch 3/15 to rename the SSC macros for dt-bindings to use generic names. These macros are not yet used in any DTS file. Swapnil Jakhade (15): phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add support for derived reference clock output .../bindings/phy/phy-cadence-sierra.yaml | 9 + .../bindings/phy/phy-cadence-torrent.yaml | 4 +- drivers/phy/cadence/phy-cadence-sierra.c | 1299 +++++++++++++++-- include/dt-bindings/phy/phy-cadence.h | 9 +- 4 files changed, 1226 insertions(+), 95 deletions(-) -- 2.26.1 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy
next reply other threads:[~2021-09-08 12:29 UTC|newest] Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-08 12:29 Swapnil Jakhade [this message] 2021-09-08 12:29 ` [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-20 23:56 ` Rob Herring 2021-09-20 23:56 ` Rob Herring 2021-09-08 12:29 ` [PATCH v2 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-20 23:57 ` Rob Herring 2021-09-20 23:57 ` Rob Herring 2021-09-08 12:29 ` [PATCH v2 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-08 12:29 ` [PATCH v2 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-20 23:57 ` Rob Herring 2021-09-20 23:57 ` Rob Herring 2021-09-08 12:29 ` [PATCH v2 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade 2021-09-08 12:29 ` Swapnil Jakhade 2021-09-15 15:13 ` [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Aswath Govindraju 2021-09-15 15:13 ` Aswath Govindraju 2021-10-11 6:50 ` Swapnil Kashinath Jakhade 2021-10-11 6:50 ` Swapnil Kashinath Jakhade
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