From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<lokeshvutla@ti.com>, <a-govindraju@ti.com>
Subject: [PATCH v2 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
Date: Wed, 8 Sep 2021 14:29:29 +0200 [thread overview]
Message-ID: <20210908122930.10224-15-sjakhade@cadence.com> (raw)
In-Reply-To: <20210908122930.10224-1-sjakhade@cadence.com>
Add clock ID for Sierra derived reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
include/dt-bindings/phy/phy-cadence.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index abc4ff81aa7b..a6c58fd46b35 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -16,5 +16,6 @@
/* Sierra */
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
+#define CDNS_SIERRA_DERIVED_REFCLK 2
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */
--
2.26.1
WARNING: multiple messages have this Message-ID (diff)
From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>,
<lokeshvutla@ti.com>, <a-govindraju@ti.com>
Subject: [PATCH v2 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
Date: Wed, 8 Sep 2021 14:29:29 +0200 [thread overview]
Message-ID: <20210908122930.10224-15-sjakhade@cadence.com> (raw)
In-Reply-To: <20210908122930.10224-1-sjakhade@cadence.com>
Add clock ID for Sierra derived reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
include/dt-bindings/phy/phy-cadence.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index abc4ff81aa7b..a6c58fd46b35 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -16,5 +16,6 @@
/* Sierra */
#define CDNS_SIERRA_PLL_CMNLC 0
#define CDNS_SIERRA_PLL_CMNLC1 1
+#define CDNS_SIERRA_DERIVED_REFCLK 2
#endif /* _DT_BINDINGS_CADENCE_SERDES_H */
--
2.26.1
--
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next prev parent reply other threads:[~2021-09-08 12:30 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 12:29 [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-20 23:56 ` Rob Herring
2021-09-20 23:56 ` Rob Herring
2021-09-08 12:29 ` [PATCH v2 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-20 23:57 ` Rob Herring
2021-09-20 23:57 ` Rob Herring
2021-09-08 12:29 ` [PATCH v2 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` [PATCH v2 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade [this message]
2021-09-08 12:29 ` [PATCH v2 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade
2021-09-20 23:57 ` Rob Herring
2021-09-20 23:57 ` Rob Herring
2021-09-08 12:29 ` [PATCH v2 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
2021-09-08 12:29 ` Swapnil Jakhade
2021-09-15 15:13 ` [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Aswath Govindraju
2021-09-15 15:13 ` Aswath Govindraju
2021-10-11 6:50 ` Swapnil Kashinath Jakhade
2021-10-11 6:50 ` Swapnil Kashinath Jakhade
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