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Wed, 8 Sep 2021 14:54:42 +0000 Received: from DESKTOP-9DR2N9S.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Wed, 8 Sep 2021 09:54:41 -0500 From: Mikita Lipski To: CC: , , , , , , , , , , , , Josip Pavic , Anthony Koo Subject: [PATCH 07/33] drm/amd/display: unblock abm when odm is enabled only on configs that support it Date: Wed, 8 Sep 2021 10:53:58 -0400 Message-ID: <20210908145424.3311-8-mikita.lipski@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908145424.3311-1-mikita.lipski@amd.com> References: <20210908145424.3311-1-mikita.lipski@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6cc3d9d1-5f30-49da-1653-08d972d8976e X-MS-TrafficTypeDiagnostic: SN6PR12MB4766: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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CAT:NONE; SFS:(4636009)(396003)(136003)(39860400002)(346002)(376002)(46966006)(36840700001)(82310400003)(2906002)(83380400001)(86362001)(36756003)(6916009)(316002)(82740400003)(36860700001)(4326008)(81166007)(54906003)(2616005)(336012)(426003)(356005)(6666004)(1076003)(47076005)(478600001)(8676002)(70206006)(70586007)(44832011)(186003)(5660300002)(26005)(16526019)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 14:54:42.7773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6cc3d9d1-5f30-49da-1653-08d972d8976e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB4766 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Josip Pavic [Why] When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30. Since the dcn31 firmware is now able to handle ABM interop with ODM, it is no longer necessary to block ABM when ODM is enabled. Since the dcn30 firmware does not handle ABM interop with ODM, leaving that combination unblocked can lead to one side of the screen appearing brighter than the other. [How] When ODM is enabled, unblock abm on dcn31 and block it on dcn30 Reviewed-by: Anthony Koo Acked-by: Mikita Lipski Signed-off-by: Josip Pavic --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 + .../gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 15 --------------- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 1 - 3 files changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index 3a5b53dd2f6d..93f32a312fee 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, .update_visual_confirm_color = dcn20_update_visual_confirm_color, + .is_abm_supported = dcn21_is_abm_supported }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c index 7feba8a0d847..2434232fb3f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c @@ -595,18 +595,3 @@ void dcn31_reset_hw_ctx_wrap( } } } - -bool dcn31_is_abm_supported(struct dc *dc, - struct dc_state *context, struct dc_stream_state *stream) -{ - int i; - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (pipe_ctx->stream == stream && - (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL)) - return true; - } - return false; -} diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c index 40011cd3c8ef..10c83f4083b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c @@ -98,7 +98,6 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .set_pipe = dcn21_set_pipe, .z10_restore = dcn31_z10_restore, .z10_save_init = dcn31_z10_save_init, - .is_abm_supported = dcn31_is_abm_supported, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .update_visual_confirm_color = dcn20_update_visual_confirm_color, }; -- 2.25.1