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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Ingo Molnar , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH 02/19] x86/msr: add AMD CPPC MSR definitions Date: Wed, 8 Sep 2021 22:59:44 +0800 Message-ID: <20210908150001.3702552-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210908150001.3702552-1-ray.huang@amd.com> References: <20210908150001.3702552-1-ray.huang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 590a14db-34a9-4488-a22e-08d972d97caf X-MS-TrafficTypeDiagnostic: MWHPR12MB1504: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yA2JjAipvYTpw6Zzy3NIMWP+UxbMRXLKy0MF84nG9SN2NE0yM3xGZBERPp2TiIZCRqcGbO8kyKCK/1i5ZQIxJrC5/eiCRuwAGjyOJSUzBVNbK5y4nZbjG5SCBdhddO5XHQhZR+FgBxT/m9sZ9NgTiljpqKW/L0f1M0EoNVhsA/r52I2OOVtXj9ciHnTXoFCmFPAVReCyXG78b594e/7HXoIRHUv1tzhJO8VuIc+EJNi2FEhX6GFfVaI4MhD+L1YiUebzrkPd4WUCevUm2/UY3pe36wfJhVXXlJcFN50Zunyj1QM1IUCLX0ciExYeclvweobpo/e8SumxzHGY5K0quY0fzUbqUWw11clS7Wv3tinHrRPVucihgtvQWvudKloT+nekpkEeXyBdj0/UrjtU1ABVIeJQXQ6jFL/gQexv61yekzmieHXQnaug17/W0/X0xUxVCB5NYsimaK8omZmUG5Ane7ImOh+R7Tq5ttHNQnu/exupusci2iwcGMtdkCALnBEQmpxCF9k5Z0X6nqfzcpCVtlHVUItsG+MLmpY02pjh058eL0yrJjeZ9eDrA6Tl57XO1Bl+X2/wE/85a0rO3lCUEGDBA4QkqJbXMPFVYB/aV8JEYKJ0YsF2ISN6PvYg13Q+CtHqSkplm9ukxUKigub2sLVsNLC6oTpmtE63uq4VqGjdCWIsDEZv6RsolYKzN4Feg/rTgbjAI/y8phuw54nfxaPEW/kxGZx2//zUYTM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(346002)(396003)(136003)(39860400002)(376002)(46966006)(36840700001)(47076005)(4326008)(16526019)(5660300002)(186003)(8676002)(7696005)(426003)(26005)(336012)(82740400003)(316002)(110136005)(70586007)(70206006)(54906003)(81166007)(2906002)(36756003)(36860700001)(1076003)(356005)(478600001)(82310400003)(6666004)(86362001)(8936002)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2021 15:01:07.3331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 590a14db-34a9-4488-a22e-08d972d97caf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1504 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..ce42e15cf303 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 -- 2.25.1