From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F547C433F5 for ; Wed, 8 Sep 2021 17:28:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7059661153 for ; Wed, 8 Sep 2021 17:28:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352467AbhIHR3i (ORCPT ); Wed, 8 Sep 2021 13:29:38 -0400 Received: from mail.kernel.org ([198.145.29.99]:60558 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230091AbhIHR3g (ORCPT ); Wed, 8 Sep 2021 13:29:36 -0400 Received: from jic23-huawei (cpc108967-cmbg20-2-0-cust86.5-4.cable.virginm.net [81.101.6.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3C68961157; Wed, 8 Sep 2021 17:28:21 +0000 (UTC) Date: Wed, 8 Sep 2021 18:31:49 +0100 From: Jonathan Cameron To: Fabrice Gasnier Cc: William Breathitt Gray , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v16 02/14] counter: stm32-timer-cnt: Provide defines for slave mode selection Message-ID: <20210908183149.468e60ac@jic23-huawei> In-Reply-To: References: X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 31 Aug 2021 15:40:37 +0200 Fabrice Gasnier wrote: > On 8/27/21 5:47 AM, William Breathitt Gray wrote: > > The STM32 timer permits configuration of the counter encoder mode via > > the slave mode control register (SMCR) slave mode selection (SMS) bits. > > This patch provides preprocessor defines for the supported encoder > > modes. > > > > Cc: Fabrice Gasnier > > Signed-off-by: William Breathitt Gray > > --- > > drivers/counter/stm32-timer-cnt.c | 16 ++++++++-------- > > include/linux/mfd/stm32-timers.h | 4 ++++ > > 2 files changed, 12 insertions(+), 8 deletions(-) > > Hi William, > > You can add my: > Reviewed-by: Fabrice Gasnier Applied. Thanks, J > > Thanks, > Fabrice > > > > > diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c > > index 3fb0debd7425..1fbc46f4ee66 100644 > > --- a/drivers/counter/stm32-timer-cnt.c > > +++ b/drivers/counter/stm32-timer-cnt.c > > @@ -93,16 +93,16 @@ static int stm32_count_function_get(struct counter_device *counter, > > regmap_read(priv->regmap, TIM_SMCR, &smcr); > > > > switch (smcr & TIM_SMCR_SMS) { > > - case 0: > > + case TIM_SMCR_SMS_SLAVE_MODE_DISABLED: > > *function = STM32_COUNT_SLAVE_MODE_DISABLED; > > return 0; > > - case 1: > > + case TIM_SMCR_SMS_ENCODER_MODE_1: > > *function = STM32_COUNT_ENCODER_MODE_1; > > return 0; > > - case 2: > > + case TIM_SMCR_SMS_ENCODER_MODE_2: > > *function = STM32_COUNT_ENCODER_MODE_2; > > return 0; > > - case 3: > > + case TIM_SMCR_SMS_ENCODER_MODE_3: > > *function = STM32_COUNT_ENCODER_MODE_3; > > return 0; > > default: > > @@ -119,16 +119,16 @@ static int stm32_count_function_set(struct counter_device *counter, > > > > switch (function) { > > case STM32_COUNT_SLAVE_MODE_DISABLED: > > - sms = 0; > > + sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; > > break; > > case STM32_COUNT_ENCODER_MODE_1: > > - sms = 1; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_1; > > break; > > case STM32_COUNT_ENCODER_MODE_2: > > - sms = 2; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_2; > > break; > > case STM32_COUNT_ENCODER_MODE_3: > > - sms = 3; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_3; > > break; > > default: > > return -EINVAL; > > diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h > > index f8db83aedb2b..5f5c43fd69dd 100644 > > --- a/include/linux/mfd/stm32-timers.h > > +++ b/include/linux/mfd/stm32-timers.h > > @@ -82,6 +82,10 @@ > > #define MAX_TIM_ICPSC 0x3 > > #define TIM_CR2_MMS_SHIFT 4 > > #define TIM_CR2_MMS2_SHIFT 20 > > +#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ > > #define TIM_SMCR_TS_SHIFT 4 > > #define TIM_BDTR_BKF_MASK 0xF > > #define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42150C433F5 for ; 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Wed, 8 Sep 2021 17:28:21 +0000 (UTC) Date: Wed, 8 Sep 2021 18:31:49 +0100 From: Jonathan Cameron To: Fabrice Gasnier Cc: William Breathitt Gray , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v16 02/14] counter: stm32-timer-cnt: Provide defines for slave mode selection Message-ID: <20210908183149.468e60ac@jic23-huawei> In-Reply-To: References: X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210908_102829_250675_BB92FCAE X-CRM114-Status: GOOD ( 21.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 31 Aug 2021 15:40:37 +0200 Fabrice Gasnier wrote: > On 8/27/21 5:47 AM, William Breathitt Gray wrote: > > The STM32 timer permits configuration of the counter encoder mode via > > the slave mode control register (SMCR) slave mode selection (SMS) bits. > > This patch provides preprocessor defines for the supported encoder > > modes. > > > > Cc: Fabrice Gasnier > > Signed-off-by: William Breathitt Gray > > --- > > drivers/counter/stm32-timer-cnt.c | 16 ++++++++-------- > > include/linux/mfd/stm32-timers.h | 4 ++++ > > 2 files changed, 12 insertions(+), 8 deletions(-) > > Hi William, > > You can add my: > Reviewed-by: Fabrice Gasnier Applied. Thanks, J > > Thanks, > Fabrice > > > > > diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c > > index 3fb0debd7425..1fbc46f4ee66 100644 > > --- a/drivers/counter/stm32-timer-cnt.c > > +++ b/drivers/counter/stm32-timer-cnt.c > > @@ -93,16 +93,16 @@ static int stm32_count_function_get(struct counter_device *counter, > > regmap_read(priv->regmap, TIM_SMCR, &smcr); > > > > switch (smcr & TIM_SMCR_SMS) { > > - case 0: > > + case TIM_SMCR_SMS_SLAVE_MODE_DISABLED: > > *function = STM32_COUNT_SLAVE_MODE_DISABLED; > > return 0; > > - case 1: > > + case TIM_SMCR_SMS_ENCODER_MODE_1: > > *function = STM32_COUNT_ENCODER_MODE_1; > > return 0; > > - case 2: > > + case TIM_SMCR_SMS_ENCODER_MODE_2: > > *function = STM32_COUNT_ENCODER_MODE_2; > > return 0; > > - case 3: > > + case TIM_SMCR_SMS_ENCODER_MODE_3: > > *function = STM32_COUNT_ENCODER_MODE_3; > > return 0; > > default: > > @@ -119,16 +119,16 @@ static int stm32_count_function_set(struct counter_device *counter, > > > > switch (function) { > > case STM32_COUNT_SLAVE_MODE_DISABLED: > > - sms = 0; > > + sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; > > break; > > case STM32_COUNT_ENCODER_MODE_1: > > - sms = 1; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_1; > > break; > > case STM32_COUNT_ENCODER_MODE_2: > > - sms = 2; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_2; > > break; > > case STM32_COUNT_ENCODER_MODE_3: > > - sms = 3; > > + sms = TIM_SMCR_SMS_ENCODER_MODE_3; > > break; > > default: > > return -EINVAL; > > diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h > > index f8db83aedb2b..5f5c43fd69dd 100644 > > --- a/include/linux/mfd/stm32-timers.h > > +++ b/include/linux/mfd/stm32-timers.h > > @@ -82,6 +82,10 @@ > > #define MAX_TIM_ICPSC 0x3 > > #define TIM_CR2_MMS_SHIFT 4 > > #define TIM_CR2_MMS2_SHIFT 20 > > +#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ > > +#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ > > #define TIM_SMCR_TS_SHIFT 4 > > #define TIM_BDTR_BKF_MASK 0xF > > #define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4) > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel