* [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets
@ 2021-09-12 14:47 Samuel Holland
2021-09-12 14:47 ` [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Samuel Holland
2021-10-06 0:17 ` [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Andre Przywara
0 siblings, 2 replies; 4+ messages in thread
From: Samuel Holland @ 2021-09-12 14:47 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Lukasz Majewski
Currently, the I2C clocks are configured in the sunxi board code. Add
the I2C clocks to the DM clock driver so they can be enabled from the
DM I2C driver using the normal uclass methods.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi/clk_a10.c | 5 +++++
drivers/clk/sunxi/clk_a10s.c | 3 +++
drivers/clk/sunxi/clk_a23.c | 6 ++++++
drivers/clk/sunxi/clk_a31.c | 8 ++++++++
drivers/clk/sunxi/clk_a64.c | 6 ++++++
drivers/clk/sunxi/clk_a80.c | 10 ++++++++++
drivers/clk/sunxi/clk_a83t.c | 6 ++++++
drivers/clk/sunxi/clk_h3.c | 6 ++++++
drivers/clk/sunxi/clk_h6.c | 10 ++++++++++
drivers/clk/sunxi/clk_h616.c | 12 ++++++++++++
drivers/clk/sunxi/clk_r40.c | 10 ++++++++++
drivers/clk/sunxi/clk_v3s.c | 4 ++++
12 files changed, 86 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 1b5de86e204..20006925f1e 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 184f61ab234..7e7b2bf7009 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 5750514a74f..87011525dcf 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 9226112f4af..2554762df9d 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
@@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 0553ffa4399..013801c7e41 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 68973d528ed..79083e846f9 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = {
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
@@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = {
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
+ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 880c7d75997..b21bd1db2c2 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f81633b92d5..5741b5e6be6 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index df93d96b3b0..0ee089295e0 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = {
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = {
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 553d7c6e550..bebefc9caa1 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = {
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = {
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ee1e86d22eb..b509bc2de62 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 29622199fdc..ba58dce5d8d 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = {
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs
2021-09-12 14:47 [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Samuel Holland
@ 2021-09-12 14:47 ` Samuel Holland
2021-10-06 0:18 ` Andre Przywara
2021-10-06 0:17 ` [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Andre Przywara
1 sibling, 1 reply; 4+ messages in thread
From: Samuel Holland @ 2021-09-12 14:47 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Lukasz Majewski
Add a driver so the clocks/resets for these peripherals (especially I2C,
RSB, and UART) can be enabled using the normal uclass methods.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/clk/sunxi/Kconfig | 14 ++++++++
drivers/clk/sunxi/Makefile | 2 ++
drivers/clk/sunxi/clk_a31_r.c | 59 +++++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk_h6_r.c | 61 +++++++++++++++++++++++++++++++++++
4 files changed, 136 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_a31_r.c
create mode 100644 drivers/clk/sunxi/clk_h6_r.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf084fa7a84..f89c7ffd42a 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -30,6 +30,13 @@ config CLK_SUN6I_A31
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
+config CLK_SUN6I_A31_R
+ bool "Clock driver for Allwinner A31 generation PRCM"
+ default SUNXI_GEN_SUN6I
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
@@ -79,6 +86,13 @@ config CLK_SUN50I_H6
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
+config CLK_SUN50I_H6_R
+ bool "Clock driver for Allwinner H6 generation PRCM"
+ default SUN50I_GEN_H6
+ help
+ This enables common clock driver support for the PRCM
+ in Allwinner H6/H616 SoCs.
+
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4f9282a8b9b..48a48a2f000 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
@@ -18,5 +19,6 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
new file mode 100644
index 00000000000..57ff98aa52b
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a31_r.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_r_gates[] = {
+ [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
+ [CLK_APB0_IR] = GATE(0x028, BIT(1)),
+ [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
+ [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
+ [CLK_APB0_UART] = GATE(0x028, BIT(4)),
+ [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
+ [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset a31_r_resets[] = {
+ [RST_APB0_IR] = RESET(0x0b0, BIT(1)),
+ [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
+ [RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
+ [RST_APB0_UART] = RESET(0x0b0, BIT(4)),
+ [RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
+};
+
+static const struct ccu_desc a31_r_ccu_desc = {
+ .gates = a31_r_gates,
+ .resets = a31_r_resets,
+};
+
+static int a31_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
+}
+
+static const struct udevice_id a31_r_clk_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun8i-h3-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-a64-r-ccu",
+ .data = (ulong)&a31_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31_r) = {
+ .name = "sun6i_a31_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = a31_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = a31_r_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
new file mode 100644
index 00000000000..91fe20c5250
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_r_gates[] = {
+ [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
+ [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
+ [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
+ [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
+ [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
+ [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
+ [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
+ [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
+};
+
+static struct ccu_reset h6_r_resets[] = {
+ [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
+ [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
+ [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
+ [RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
+ [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
+ [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
+ [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
+ [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
+};
+
+static const struct ccu_desc h6_r_ccu_desc = {
+ .gates = h6_r_gates,
+ .resets = h6_r_resets,
+};
+
+static int h6_r_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
+}
+
+static const struct udevice_id h6_r_clk_ids[] = {
+ { .compatible = "allwinner,sun50i-h6-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { .compatible = "allwinner,sun50i-h616-r-ccu",
+ .data = (ulong)&h6_r_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun6i_h6_r) = {
+ .name = "sun6i_h6_r_ccu",
+ .id = UCLASS_CLK,
+ .of_match = h6_r_clk_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops = &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = h6_r_clk_bind,
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets
2021-09-12 14:47 [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Samuel Holland
2021-09-12 14:47 ` [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Samuel Holland
@ 2021-10-06 0:17 ` Andre Przywara
1 sibling, 0 replies; 4+ messages in thread
From: Andre Przywara @ 2021-10-06 0:17 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Lukasz Majewski
On Sun, 12 Sep 2021 09:47:24 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Currently, the I2C clocks are configured in the sunxi board code. Add
> the I2C clocks to the DM clock driver so they can be enabled from the
> DM I2C driver using the normal uclass methods.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared against the kernel's drivers/clk/sunxi-ng/ccu-*.c.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks,
Andre
> ---
>
> drivers/clk/sunxi/clk_a10.c | 5 +++++
> drivers/clk/sunxi/clk_a10s.c | 3 +++
> drivers/clk/sunxi/clk_a23.c | 6 ++++++
> drivers/clk/sunxi/clk_a31.c | 8 ++++++++
> drivers/clk/sunxi/clk_a64.c | 6 ++++++
> drivers/clk/sunxi/clk_a80.c | 10 ++++++++++
> drivers/clk/sunxi/clk_a83t.c | 6 ++++++
> drivers/clk/sunxi/clk_h3.c | 6 ++++++
> drivers/clk/sunxi/clk_h6.c | 10 ++++++++++
> drivers/clk/sunxi/clk_h616.c | 12 ++++++++++++
> drivers/clk/sunxi/clk_r40.c | 10 ++++++++++
> drivers/clk/sunxi/clk_v3s.c | 4 ++++
> 12 files changed, 86 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
> index 1b5de86e204..20006925f1e 100644
> --- a/drivers/clk/sunxi/clk_a10.c
> +++ b/drivers/clk/sunxi/clk_a10.c
> @@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = {
>
> [CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
>
> + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> + [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
> + [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
> [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
> [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
> [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
> index 184f61ab234..7e7b2bf7009 100644
> --- a/drivers/clk/sunxi/clk_a10s.c
> +++ b/drivers/clk/sunxi/clk_a10s.c
> @@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = {
> [CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
> [CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
>
> + [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
> [CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
> [CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
> [CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
> index 5750514a74f..87011525dcf 100644
> --- a/drivers/clk/sunxi/clk_a23.c
> +++ b/drivers/clk/sunxi/clk_a23.c
> @@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = {
> [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
> [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = {
> [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
> [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
> index 9226112f4af..2554762df9d 100644
> --- a/drivers/clk/sunxi/clk_a31.c
> +++ b/drivers/clk/sunxi/clk_a31.c
> @@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = {
> [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
> [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
>
> + [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
> + [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
> [CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
> [CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
> [CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
> @@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = {
> [RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
> [RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
>
> + [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
> + [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
> [RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
> [RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
> [RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
> index 0553ffa4399..013801c7e41 100644
> --- a/drivers/clk/sunxi/clk_a64.c
> +++ b/drivers/clk/sunxi/clk_a64.c
> @@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = {
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
> [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = {
> [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
> [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
> index 68973d528ed..79083e846f9 100644
> --- a/drivers/clk/sunxi/clk_a80.c
> +++ b/drivers/clk/sunxi/clk_a80.c
> @@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = {
> [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
> [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
>
> + [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
> + [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
> + [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
> [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x594, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x594, BIT(18)),
> @@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = {
> [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
> [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
>
> + [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
> + [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
> + [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
> [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
> [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
> [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
> index 880c7d75997..b21bd1db2c2 100644
> --- a/drivers/clk/sunxi/clk_a83t.c
> +++ b/drivers/clk/sunxi/clk_a83t.c
> @@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = {
> [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
> [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = {
> [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
> [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
> index f81633b92d5..5741b5e6be6 100644
> --- a/drivers/clk/sunxi/clk_h3.c
> +++ b/drivers/clk/sunxi/clk_h3.c
> @@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = {
> [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
> [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = {
>
> [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
> index df93d96b3b0..0ee089295e0 100644
> --- a/drivers/clk/sunxi/clk_h6.c
> +++ b/drivers/clk/sunxi/clk_h6.c
> @@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = {
> [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
> [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
>
> + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
> + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
> +
> [CLK_SPI0] = GATE(0x940, BIT(31)),
> [CLK_SPI1] = GATE(0x944, BIT(31)),
>
> @@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = {
> [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
> [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
>
> + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
> + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
> + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
> + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
> +
> [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
> [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
>
> diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
> index 553d7c6e550..bebefc9caa1 100644
> --- a/drivers/clk/sunxi/clk_h616.c
> +++ b/drivers/clk/sunxi/clk_h616.c
> @@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = {
> [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
> [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
>
> + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
> + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
> + [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
> +
> [CLK_SPI0] = GATE(0x940, BIT(31)),
> [CLK_SPI1] = GATE(0x944, BIT(31)),
>
> @@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = {
> [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
> [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
>
> + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
> + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
> + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
> + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
> + [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
> +
> [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
> [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
>
> diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
> index ee1e86d22eb..b509bc2de62 100644
> --- a/drivers/clk/sunxi/clk_r40.c
> +++ b/drivers/clk/sunxi/clk_r40.c
> @@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = {
>
> [CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> + [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
> + [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
> + [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = {
>
> [RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> + [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
> + [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
> + [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
> diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
> index 29622199fdc..ba58dce5d8d 100644
> --- a/drivers/clk/sunxi/clk_v3s.c
> +++ b/drivers/clk/sunxi/clk_v3s.c
> @@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
> [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
> [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
>
> + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
> + [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
> [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
> [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
> [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
> @@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = {
> [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
> [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
>
> + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
> + [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
> [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
> [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
> [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs
2021-09-12 14:47 ` [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Samuel Holland
@ 2021-10-06 0:18 ` Andre Przywara
0 siblings, 0 replies; 4+ messages in thread
From: Andre Przywara @ 2021-10-06 0:18 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Lukasz Majewski
On Sun, 12 Sep 2021 09:47:25 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Add a driver so the clocks/resets for these peripherals (especially I2C,
> RSB, and UART) can be enabled using the normal uclass methods.
>
Compared against the respective Linux bits.
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> drivers/clk/sunxi/Kconfig | 14 ++++++++
> drivers/clk/sunxi/Makefile | 2 ++
> drivers/clk/sunxi/clk_a31_r.c | 59 +++++++++++++++++++++++++++++++++
> drivers/clk/sunxi/clk_h6_r.c | 61 +++++++++++++++++++++++++++++++++++
> 4 files changed, 136 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk_a31_r.c
> create mode 100644 drivers/clk/sunxi/clk_h6_r.c
>
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index bf084fa7a84..f89c7ffd42a 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -30,6 +30,13 @@ config CLK_SUN6I_A31
> This enables common clock driver support for platforms based
> on Allwinner A31/A31s SoC.
>
> +config CLK_SUN6I_A31_R
> + bool "Clock driver for Allwinner A31 generation PRCM"
> + default SUNXI_GEN_SUN6I
> + help
> + This enables common clock driver support for the PRCM
> + in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
> +
> config CLK_SUN8I_A23
> bool "Clock driver for Allwinner A23/A33"
> default MACH_SUN8I_A23 || MACH_SUN8I_A33
> @@ -79,6 +86,13 @@ config CLK_SUN50I_H6
> This enables common clock driver support for platforms based
> on Allwinner H6 SoC.
>
> +config CLK_SUN50I_H6_R
> + bool "Clock driver for Allwinner H6 generation PRCM"
> + default SUN50I_GEN_H6
> + help
> + This enables common clock driver support for the PRCM
> + in Allwinner H6/H616 SoCs.
> +
> config CLK_SUN50I_H616
> bool "Clock driver for Allwinner H616"
> default MACH_SUN50I_H616
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 4f9282a8b9b..48a48a2f000 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
> obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
> obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
> obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
> +obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
> obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
> obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
> obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
> @@ -18,5 +19,6 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
> obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
> obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
> obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
> +obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
> obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
> obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
> diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
> new file mode 100644
> index 00000000000..57ff98aa52b
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_a31_r.c
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) Samuel Holland <samuel@sholland.org>
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <asm/arch/ccu.h>
> +#include <dt-bindings/clock/sun8i-r-ccu.h>
> +#include <dt-bindings/reset/sun8i-r-ccu.h>
> +#include <linux/bitops.h>
> +
> +static struct ccu_clk_gate a31_r_gates[] = {
> + [CLK_APB0_PIO] = GATE(0x028, BIT(0)),
> + [CLK_APB0_IR] = GATE(0x028, BIT(1)),
> + [CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
> + [CLK_APB0_RSB] = GATE(0x028, BIT(3)),
> + [CLK_APB0_UART] = GATE(0x028, BIT(4)),
> + [CLK_APB0_I2C] = GATE(0x028, BIT(6)),
> + [CLK_APB0_TWD] = GATE(0x028, BIT(7)),
> +};
> +
> +static struct ccu_reset a31_r_resets[] = {
> + [RST_APB0_IR] = RESET(0x0b0, BIT(1)),
> + [RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
> + [RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
> + [RST_APB0_UART] = RESET(0x0b0, BIT(4)),
> + [RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
> +};
> +
> +static const struct ccu_desc a31_r_ccu_desc = {
> + .gates = a31_r_gates,
> + .resets = a31_r_resets,
> +};
> +
> +static int a31_r_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
> +}
> +
> +static const struct udevice_id a31_r_clk_ids[] = {
> + { .compatible = "allwinner,sun8i-a83t-r-ccu",
> + .data = (ulong)&a31_r_ccu_desc },
> + { .compatible = "allwinner,sun8i-h3-r-ccu",
> + .data = (ulong)&a31_r_ccu_desc },
> + { .compatible = "allwinner,sun50i-a64-r-ccu",
> + .data = (ulong)&a31_r_ccu_desc },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_sun6i_a31_r) = {
> + .name = "sun6i_a31_r_ccu",
> + .id = UCLASS_CLK,
> + .of_match = a31_r_clk_ids,
> + .priv_auto = sizeof(struct ccu_priv),
> + .ops = &sunxi_clk_ops,
> + .probe = sunxi_clk_probe,
> + .bind = a31_r_clk_bind,
> +};
> diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
> new file mode 100644
> index 00000000000..91fe20c5250
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk_h6_r.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) Samuel Holland <samuel@sholland.org>
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <asm/arch/ccu.h>
> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> +#include <linux/bitops.h>
> +
> +static struct ccu_clk_gate h6_r_gates[] = {
> + [CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
> + [CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
> + [CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
> + [CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
> + [CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
> + [CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
> + [CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
> + [CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
> +};
> +
> +static struct ccu_reset h6_r_resets[] = {
> + [RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
> + [RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
> + [RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
> + [RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
> + [RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
> + [RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
> + [RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
> + [RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
> +};
> +
> +static const struct ccu_desc h6_r_ccu_desc = {
> + .gates = h6_r_gates,
> + .resets = h6_r_resets,
> +};
> +
> +static int h6_r_clk_bind(struct udevice *dev)
> +{
> + return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
> +}
> +
> +static const struct udevice_id h6_r_clk_ids[] = {
> + { .compatible = "allwinner,sun50i-h6-r-ccu",
> + .data = (ulong)&h6_r_ccu_desc },
> + { .compatible = "allwinner,sun50i-h616-r-ccu",
> + .data = (ulong)&h6_r_ccu_desc },
> + { }
> +};
> +
> +U_BOOT_DRIVER(clk_sun6i_h6_r) = {
> + .name = "sun6i_h6_r_ccu",
> + .id = UCLASS_CLK,
> + .of_match = h6_r_clk_ids,
> + .priv_auto = sizeof(struct ccu_priv),
> + .ops = &sunxi_clk_ops,
> + .probe = sunxi_clk_probe,
> + .bind = h6_r_clk_bind,
> +};
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-10-06 0:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-12 14:47 [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Samuel Holland
2021-09-12 14:47 ` [PATCH 2/2] clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Samuel Holland
2021-10-06 0:18 ` Andre Przywara
2021-10-06 0:17 ` [PATCH 1/2] clk: sunxi: Add support for I2C gates/resets Andre Przywara
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