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[83.52.55.21]) by smtp.gmail.com with ESMTPSA id o12sm4262854wms.15.2021.09.12.10.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Sep 2021 10:27:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v4 00/30] accel: Move has_work() from SysemuCPUOps to AccelOpsClass Date: Sun, 12 Sep 2021 19:27:01 +0200 Message-Id: <20210912172731.789788-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Missing review:=0D - 0001-accel-tcg-Restrict-cpu_handle_halt-to-sysemu.patch=0D - 0020-target-ppc-Introduce-PowerPCCPUClass-has_work.patch=0D - 0021-target-ppc-Restrict-has_work-handlers-to-sysemu-and-.patch=0D - 0026-target-sparc-Remove-pointless-use-of-CONFIG_TCG-defi.patch=0D =0D Hi,=0D =0D CPU has_work() is a per-accelerator handler. This series=0D - explicit the KVM / WHPX implementations=0D - moves TCG implementations in AccelOpsClass=0D - explicit missing implementations (returning 'false').=0D =0D Since v3:=0D - Remove pointless CONFIG_TCG uses (rth)=0D - Rework PPC patches, still using indirection=0D =0D Since v2:=0D - Full rewrite, no more RFC.=0D =0D Philippe Mathieu-Daud=C3=A9 (30):=0D accel/tcg: Restrict cpu_handle_halt() to sysemu=0D hw/core: Restrict cpu_has_work() to sysemu=0D hw/core: Un-inline cpu_has_work()=0D sysemu: Introduce AccelOpsClass::has_work()=0D accel/kvm: Implement AccelOpsClass::has_work()=0D accel/whpx: Implement AccelOpsClass::has_work()=0D accel/tcg: Implement AccelOpsClass::has_work() as stub=0D target/alpha: Restrict has_work() handler to sysemu=0D target/arm: Restrict has_work() handler to sysemu and TCG=0D target/avr: Restrict has_work() handler to sysemu=0D target/cris: Restrict has_work() handler to sysemu=0D target/hexagon: Remove unused has_work() handler=0D target/hppa: Restrict has_work() handler to sysemu=0D target/i386: Restrict has_work() handler to sysemu and TCG=0D target/m68k: Restrict has_work() handler to sysemu=0D target/microblaze: Restrict has_work() handler to sysemu=0D target/mips: Restrict has_work() handler to sysemu and TCG=0D target/nios2: Restrict has_work() handler to sysemu=0D target/openrisc: Restrict has_work() handler to sysemu=0D target/ppc: Introduce PowerPCCPUClass::has_work()=0D target/ppc: Restrict has_work() handlers to sysemu and TCG=0D target/riscv: Restrict has_work() handler to sysemu and TCG=0D target/rx: Restrict has_work() handler to sysemu=0D target/s390x: Restrict has_work() handler to sysemu and TCG=0D target/sh4: Restrict has_work() handler to sysemu=0D target/sparc: Remove pointless use of CONFIG_TCG definition=0D target/sparc: Restrict has_work() handler to sysemu=0D target/tricore: Restrict has_work() handler to sysemu=0D target/xtensa: Restrict has_work() handler to sysemu=0D accel: Add missing AccelOpsClass::has_work() and drop SysemuCPUOps one=0D =0D include/hw/core/cpu.h | 28 +++++++++--------------=0D include/hw/core/tcg-cpu-ops.h | 4 ++++=0D include/sysemu/accel-ops.h | 5 +++++=0D target/ppc/cpu-qom.h | 3 +++=0D accel/hvf/hvf-accel-ops.c | 6 +++++=0D accel/kvm/kvm-accel-ops.c | 6 +++++=0D accel/qtest/qtest.c | 6 +++++=0D accel/tcg/cpu-exec.c | 6 +++--=0D accel/tcg/tcg-accel-ops.c | 12 ++++++++++=0D accel/xen/xen-all.c | 6 +++++=0D hw/core/cpu-common.c | 6 -----=0D softmmu/cpus.c | 10 ++++++---=0D target/alpha/cpu.c | 4 +++-=0D target/arm/cpu.c | 7 ++++--=0D target/avr/cpu.c | 2 +-=0D target/cris/cpu.c | 4 +++-=0D target/hexagon/cpu.c | 6 -----=0D target/hppa/cpu.c | 4 +++-=0D target/i386/cpu.c | 6 -----=0D target/i386/hax/hax-accel-ops.c | 6 +++++=0D target/i386/nvmm/nvmm-accel-ops.c | 6 +++++=0D target/i386/tcg/tcg-cpu.c | 8 ++++++-=0D target/i386/whpx/whpx-accel-ops.c | 6 +++++=0D target/m68k/cpu.c | 4 +++-=0D target/microblaze/cpu.c | 8 +++----=0D target/mips/cpu.c | 4 +++-=0D target/nios2/cpu.c | 4 +++-=0D target/openrisc/cpu.c | 4 +++-=0D target/ppc/cpu_init.c | 37 ++++++++++++++++++++++---------=0D target/riscv/cpu.c | 8 +++----=0D target/rx/cpu.c | 4 +++-=0D target/s390x/cpu.c | 4 +++-=0D target/sh4/cpu.c | 5 +++--=0D target/sparc/cpu.c | 6 ++---=0D target/tricore/cpu.c | 6 ++++-=0D target/xtensa/cpu.c | 14 ++++++------=0D 36 files changed, 179 insertions(+), 86 deletions(-)=0D =0D -- =0D 2.31.1=0D =0D