From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20000C433EF for ; Mon, 13 Sep 2021 23:53:55 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F7576112E for ; Mon, 13 Sep 2021 23:53:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6F7576112E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 65C008397D; Tue, 14 Sep 2021 01:53:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 2B21582D74; Tue, 14 Sep 2021 01:53:46 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 038888396A for ; Tue, 14 Sep 2021 01:53:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E8AB6D; Mon, 13 Sep 2021 16:53:37 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E8DE3F719; Mon, 13 Sep 2021 16:53:36 -0700 (PDT) Date: Tue, 14 Sep 2021 00:53:33 +0100 From: Andre Przywara To: Samuel Holland Cc: u-boot@lists.denx.de, Jagan Teki Subject: Re: [PATCH 3/3] sunxi: gpio: Remove bank-specific size macros Message-ID: <20210914005333.54ae5b76@slackpad.fritz.box> In-Reply-To: <20210911215049.5840-4-samuel@sholland.org> References: <20210911215049.5840-1-samuel@sholland.org> <20210911215049.5840-4-samuel@sholland.org> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Sat, 11 Sep 2021 16:50:49 -0500 Samuel Holland wrote: > Since the beginning, all banks have had space for 32 pins, even when > not all pins were implemented. Let's use a single constant for the GPIO > bank size here, like the GPIO driver is already doing. Yeah, I always found some code in there a bit over the top, thanks for cleaning this up. > Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Cheers, Andre > --- > > arch/arm/include/asm/arch-sunxi/gpio.h | 14 ++------------ > drivers/gpio/sunxi_gpio.c | 2 -- > 2 files changed, 2 insertions(+), 14 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index c93c051a19f..cd5e85988b1 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -93,20 +93,10 @@ struct sunxi_gpio_reg { > #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) > > /* GPIO bank sizes */ > -#define SUNXI_GPIO_A_NR 32 > -#define SUNXI_GPIO_B_NR 32 > -#define SUNXI_GPIO_C_NR 32 > -#define SUNXI_GPIO_D_NR 32 > -#define SUNXI_GPIO_E_NR 32 > -#define SUNXI_GPIO_F_NR 32 > -#define SUNXI_GPIO_G_NR 32 > -#define SUNXI_GPIO_H_NR 32 > -#define SUNXI_GPIO_I_NR 32 > -#define SUNXI_GPIO_L_NR 32 > -#define SUNXI_GPIO_M_NR 32 > +#define SUNXI_GPIOS_PER_BANK 32 > > #define SUNXI_GPIO_NEXT(__gpio) \ > - ((__gpio##_START) + (__gpio##_NR) + 0) > + ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) > > enum sunxi_gpio_number { > SUNXI_GPIO_A_START = 0, > diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c > index 7ce3ef73b46..ed26eb011f4 100644 > --- a/drivers/gpio/sunxi_gpio.c > +++ b/drivers/gpio/sunxi_gpio.c > @@ -19,8 +19,6 @@ > #include > #include > > -#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR > - > struct sunxi_gpio_plat { > struct sunxi_gpio *regs; > const char *bank_name; /* Name of bank, e.g. "B" */