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From: Iago Toral Quiroga <itoral@igalia.com>
To: dri-devel@lists.freedesktop.org
Cc: mwen@igalia.com
Subject: [PATCH] drm/v3d: fix wait for TMU write combiner flush
Date: Tue, 14 Sep 2021 07:55:49 +0200	[thread overview]
Message-ID: <20210914055549.4340-1-itoral@igalia.com> (raw)

The hardware sets the TMUWCF bit back to 0 when the TMU write
combiner flush completes so we should be checking for that instead
of the L2TFLS bit.

Fixes spurious Vulkan CTS failures in:
dEQP-VK.binding_model.descriptorset_random.*
---
 drivers/gpu/drm/v3d/v3d_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c
index a3529809d547..5159f544bc16 100644
--- a/drivers/gpu/drm/v3d/v3d_gem.c
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
@@ -197,7 +197,7 @@ v3d_clean_caches(struct v3d_dev *v3d)
 
 	V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
 	if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
-		       V3D_L2TCACTL_L2TFLS), 100)) {
+		       V3D_L2TCACTL_TMUWCF), 100)) {
 		DRM_ERROR("Timeout waiting for L1T write combiner flush\n");
 	}
 
-- 
2.25.1


             reply	other threads:[~2021-09-14  5:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-14  5:55 Iago Toral Quiroga [this message]
2021-09-15  8:57 ` [PATCH] drm/v3d: fix wait for TMU write combiner flush Melissa Wen
2021-09-15  9:54   ` Iago Toral
2021-09-15 10:05   ` [PATCH v2] " Iago Toral Quiroga
2021-09-15 17:54     ` Melissa Wen

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