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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id o10sm11472466wrc.16.2021.09.14.05.07.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 05:07:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/3] target/arm: Set FPSCR.LTPSIZE for user-mode Date: Tue, 14 Sep 2021 13:07:22 +0100 Message-Id: <20210914120725.24992-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christophe Lyon Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset fixes https://gitlab.com/qemu-project/qemu/-/issues/613 which is a bug where we weren't setting FPSCR.LTPSIZE correctly out of reset for the user-mode emulator. The effect is that when using an M-profile CPU with the low-overhead-branch or MVE extensions (ie the Cortex-M55) with the linux-user QEMU the 'LE' instruction would take a UserFault and MVE instructions would be incorrectly predicated. This is the result of some over-exuberant ifdeffery in the arm_cpu_reset() function. Patch 1 fixes that so that most of the M-profile-specific reset handling is not ifdeffed, and when we're in user mode we specifically set the FPU state up cleanly. Patches 2 and 3 are just follow-on tidyup. Christophe, if you are in a position to test this series with: M55 (has Security, MVE and LOB) M33 (has Security extension but not MVE/LOB) M7 or M4 (no Security, but does have FPU) that would be ideal. I don't really have much in the way of test cases for usermode to hand, so it's possible that I forgot something in the init of the FPU state that might break one of those combinations. (It does fix the test case attached to the bug report.) thanks -- PMM Peter Maydell (3): target/arm: Don't skip M-profile reset entirely in user mode target/arm: Always clear exclusive monitor on reset target/arm: Consolidate ifdef blocks in reset target/arm/cpu.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) -- 2.20.1