* [Intel-gfx] [PATCH v3 0/6] drm/i915: Suspend / resume backup- and restore of LMEM.
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Implement backup and restore of LMEM during suspend / resume.
What complicates things a bit is handling of pinned LMEM memory during
suspend and the fact that we might be dealing with unmappable LMEM in
the future, which makes us want to restrict the number of pinned objects that
need memcpy resume.
The first two patches are prereq patches implementing object content copy
and a generic means of iterating through all objects in a region.
The third patch adds the backup / recover / restore functions and the
two last patches deal with restricting the number of objects we need to
use memcpy for.
v2:
- Some polishing of patch 4/6, see patch commit message for details (Chris
Wilson)
- Rework of patch 3/6.
v3:
- Comment changes in patch 2/6 (Matthew Auld)
- A number of changes to patch 3/6, see commit message.
- Slightly reword comment in patch 5/6. (Matthew Auld).
Thomas Hellström (6):
drm/i915/ttm: Implement a function to copy the contents of two
TTM-based objects
drm/i915/gem: Implement a function to process all gem objects of a
region
drm/i915 Implement LMEM backup and restore for suspend / resume
drm/i915/gt: Register the migrate contexts with their engines
drm/i915: Don't back up pinned LMEM context images and rings during
suspend
drm/i915: Reduce the number of objects subject to memcpy recover
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 21 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 95 +++++++-
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 98 +++++++--
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 14 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 208 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 24 ++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +
.../drm/i915/gt/intel_execlists_submission.c | 2 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +-
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +
drivers/gpu/drm/i915/gt/mock_engine.c | 2 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
38 files changed, 652 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
--
2.31.1
^ permalink raw reply [flat|nested] 37+ messages in thread* [PATCH v3 1/6] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
When backing up or restoring contents of pinned objects at suspend /
resume time we need to allocate a new object as the backup. Add a function
to facilitate copies between the two. Some data needs to be copied before
the migration context is ready for operation, so make sure we can
disable accelerated copies.
v2:
- Fix a missing return value check (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 69 +++++++++++++++++++++----
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 ++
2 files changed, 64 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index aefaf9293005..a75bb94d029b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -431,6 +431,7 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
bool clear,
struct ttm_resource *dst_mem,
+ struct ttm_tt *dst_ttm,
struct sg_table *dst_st)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
@@ -440,14 +441,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
- struct ttm_tt *ttm = bo->ttm;
+ struct ttm_tt *src_ttm = bo->ttm;
enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
if (clear) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
@@ -464,10 +465,10 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(src_ttm) :
obj->ttm.cached_io_st;
- src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
+ src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
NULL, src_st->sgl, src_level,
@@ -487,11 +488,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
struct ttm_resource *dst_mem,
- struct sg_table *dst_st)
+ struct ttm_tt *dst_ttm,
+ struct sg_table *dst_st,
+ bool allow_accel)
{
- int ret;
+ int ret = -EINVAL;
- ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_st);
+ if (allow_accel)
+ ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_ttm, dst_st);
if (ret) {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct intel_memory_region *dst_reg, *src_reg;
@@ -506,7 +510,7 @@ static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
GEM_BUG_ON(!dst_reg || !src_reg);
dst_iter = !cpu_maps_iomem(dst_mem) ?
- ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
+ ttm_kmap_iter_tt_init(&_dst_iter.tt, dst_ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
@@ -561,7 +565,7 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
clear = !cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
if (!(clear && ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)))
- __i915_ttm_move(bo, clear, dst_mem, dst_st);
+ __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_st, true);
ttm_bo_move_sync_cleanup(bo, dst_mem);
i915_ttm_adjust_domains_after_move(obj);
@@ -972,3 +976,50 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
intel_memory_region_set_name(mr, "system-ttm");
return mr;
}
+
+/**
+ * i915_gem_obj_copy_ttm - Copy the contents of one ttm-based gem object to
+ * another
+ * @dst: The destination object
+ * @src: The source object
+ * @allow_accel: Allow using the blitter. Otherwise TTM memcpy is used.
+ * @intr: Whether to perform waits interruptible:
+ *
+ * Note: The caller is responsible for assuring that the underlying
+ * TTM objects are populated if needed and locked.
+ *
+ * Return: Zero on success. Negative error code on error. If @intr == true,
+ * then it may return -ERESTARTSYS or -EINTR.
+ */
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr)
+{
+ struct ttm_buffer_object *dst_bo = i915_gem_to_ttm(dst);
+ struct ttm_buffer_object *src_bo = i915_gem_to_ttm(src);
+ struct ttm_operation_ctx ctx = {
+ .interruptible = intr,
+ };
+ struct sg_table *dst_st;
+ int ret;
+
+ assert_object_held(dst);
+ assert_object_held(src);
+
+ /*
+ * Sync for now. This will change with async moves.
+ */
+ ret = ttm_bo_wait_ctx(dst_bo, &ctx);
+ if (!ret)
+ ret = ttm_bo_wait_ctx(src_bo, &ctx);
+ if (ret)
+ return ret;
+
+ dst_st = gpu_binds_iomem(dst_bo->resource) ?
+ dst->ttm.cached_io_st : i915_ttm_tt_get_st(dst_bo->ttm);
+
+ __i915_ttm_move(src_bo, false, dst_bo->resource, dst_bo->ttm,
+ dst_st, allow_accel);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 40927f67b6d9..34ac78d47b0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -46,4 +46,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
resource_size_t size,
resource_size_t page_size,
unsigned int flags);
+
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 1/6] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
When backing up or restoring contents of pinned objects at suspend /
resume time we need to allocate a new object as the backup. Add a function
to facilitate copies between the two. Some data needs to be copied before
the migration context is ready for operation, so make sure we can
disable accelerated copies.
v2:
- Fix a missing return value check (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 69 +++++++++++++++++++++----
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 ++
2 files changed, 64 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index aefaf9293005..a75bb94d029b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -431,6 +431,7 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
bool clear,
struct ttm_resource *dst_mem,
+ struct ttm_tt *dst_ttm,
struct sg_table *dst_st)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
@@ -440,14 +441,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
- struct ttm_tt *ttm = bo->ttm;
+ struct ttm_tt *src_ttm = bo->ttm;
enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
if (clear) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
@@ -464,10 +465,10 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(src_ttm) :
obj->ttm.cached_io_st;
- src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
+ src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
NULL, src_st->sgl, src_level,
@@ -487,11 +488,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
struct ttm_resource *dst_mem,
- struct sg_table *dst_st)
+ struct ttm_tt *dst_ttm,
+ struct sg_table *dst_st,
+ bool allow_accel)
{
- int ret;
+ int ret = -EINVAL;
- ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_st);
+ if (allow_accel)
+ ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_ttm, dst_st);
if (ret) {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct intel_memory_region *dst_reg, *src_reg;
@@ -506,7 +510,7 @@ static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
GEM_BUG_ON(!dst_reg || !src_reg);
dst_iter = !cpu_maps_iomem(dst_mem) ?
- ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
+ ttm_kmap_iter_tt_init(&_dst_iter.tt, dst_ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
@@ -561,7 +565,7 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
clear = !cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
if (!(clear && ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)))
- __i915_ttm_move(bo, clear, dst_mem, dst_st);
+ __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_st, true);
ttm_bo_move_sync_cleanup(bo, dst_mem);
i915_ttm_adjust_domains_after_move(obj);
@@ -972,3 +976,50 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
intel_memory_region_set_name(mr, "system-ttm");
return mr;
}
+
+/**
+ * i915_gem_obj_copy_ttm - Copy the contents of one ttm-based gem object to
+ * another
+ * @dst: The destination object
+ * @src: The source object
+ * @allow_accel: Allow using the blitter. Otherwise TTM memcpy is used.
+ * @intr: Whether to perform waits interruptible:
+ *
+ * Note: The caller is responsible for assuring that the underlying
+ * TTM objects are populated if needed and locked.
+ *
+ * Return: Zero on success. Negative error code on error. If @intr == true,
+ * then it may return -ERESTARTSYS or -EINTR.
+ */
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr)
+{
+ struct ttm_buffer_object *dst_bo = i915_gem_to_ttm(dst);
+ struct ttm_buffer_object *src_bo = i915_gem_to_ttm(src);
+ struct ttm_operation_ctx ctx = {
+ .interruptible = intr,
+ };
+ struct sg_table *dst_st;
+ int ret;
+
+ assert_object_held(dst);
+ assert_object_held(src);
+
+ /*
+ * Sync for now. This will change with async moves.
+ */
+ ret = ttm_bo_wait_ctx(dst_bo, &ctx);
+ if (!ret)
+ ret = ttm_bo_wait_ctx(src_bo, &ctx);
+ if (ret)
+ return ret;
+
+ dst_st = gpu_binds_iomem(dst_bo->resource) ?
+ dst->ttm.cached_io_st : i915_ttm_tt_get_st(dst_bo->ttm);
+
+ __i915_ttm_move(src_bo, false, dst_bo->resource, dst_bo->ttm,
+ dst_st, allow_accel);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 40927f67b6d9..34ac78d47b0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -46,4 +46,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
resource_size_t size,
resource_size_t page_size,
unsigned int flags);
+
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 1/6] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-16 10:17 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-16 10:17 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> When backing up or restoring contents of pinned objects at suspend /
> resume time we need to allocate a new object as the backup. Add a function
> to facilitate copies between the two. Some data needs to be copied before
> the migration context is ready for operation, so make sure we can
> disable accelerated copies.
>
> v2:
> - Fix a missing return value check (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/6] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
@ 2021-09-16 10:17 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-16 10:17 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> When backing up or restoring contents of pinned objects at suspend /
> resume time we need to allocate a new object as the backup. Add a function
> to facilitate copies between the two. Some data needs to be copied before
> the migration context is ready for operation, so make sure we can
> disable accelerated copies.
>
> v2:
> - Fix a missing return value check (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 2/6] drm/i915/gem: Implement a function to process all gem objects of a region
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
An upcoming common pattern is to traverse the region object list and
perform certain actions on all objects in a region. It's a little tricky
to get the list locking right, in particular since a gem object may
change region unless it's pinned or the object lock is held.
Define a function that does this for us and that takes an argument that
defines the action to be performed on each object.
v3:
- Improve structure documentation a bit (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++++++++++
2 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 1f557b2178ed..a016ccec36f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -80,3 +80,73 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
i915_gem_object_free(obj);
return ERR_PTR(err);
}
+
+/**
+ * i915_gem_process_region - Iterate over all objects of a region using ops
+ * to process and optionally skip objects
+ * @mr: The memory region
+ * @apply: ops and private data
+ *
+ * This function can be used to iterate over the regions object list,
+ * checking whether to skip objects, and, if not, lock the objects and
+ * process them using the supplied ops. Note that this function temporarily
+ * removes objects from the region list while iterating, so that if run
+ * concurrently with itself may not iterate over all objects.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply)
+{
+ const struct i915_gem_apply_to_region_ops *ops = apply->ops;
+ struct drm_i915_gem_object *obj;
+ struct list_head still_in_list;
+ int ret = 0;
+
+ /*
+ * In the future, a non-NULL apply->ww could mean the caller is
+ * already in a locking transaction and provides its own context.
+ */
+ GEM_WARN_ON(apply->ww);
+
+ INIT_LIST_HEAD(&still_in_list);
+ mutex_lock(&mr->objects.lock);
+ for (;;) {
+ struct i915_gem_ww_ctx ww;
+
+ obj = list_first_entry_or_null(&mr->objects.list, typeof(*obj),
+ mm.region_link);
+ if (!obj)
+ break;
+
+ list_move_tail(&obj->mm.region_link, &still_in_list);
+ if (!kref_get_unless_zero(&obj->base.refcount))
+ continue;
+
+ /*
+ * Note: Someone else might be migrating the object at this
+ * point. The object's region is not stable until we lock
+ * the object.
+ */
+ mutex_unlock(&mr->objects.lock);
+ apply->ww = &ww;
+ for_i915_gem_ww(&ww, ret, apply->interruptible) {
+ ret = i915_gem_object_lock(obj, apply->ww);
+ if (ret)
+ continue;
+
+ if (obj->mm.region == mr)
+ ret = ops->process_obj(apply, obj);
+ /* Implicit object unlock */
+ }
+
+ i915_gem_object_put(obj);
+ mutex_lock(&mr->objects.lock);
+ if (ret)
+ break;
+ }
+ list_splice_tail(&still_in_list, &mr->objects.list);
+ mutex_unlock(&mr->objects.lock);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index 1008e580a89a..fcaa12d657d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -12,6 +12,41 @@ struct intel_memory_region;
struct drm_i915_gem_object;
struct sg_table;
+struct i915_gem_apply_to_region;
+
+/**
+ * struct i915_gem_apply_to_region_ops - ops to use when iterating over all
+ * region objects.
+ */
+struct i915_gem_apply_to_region_ops {
+ /**
+ * process_obj - Process the current object
+ * @apply: Embed this for private data.
+ * @obj: The current object.
+ *
+ * Note that if this function is part of a ww transaction, and
+ * if returns -EDEADLK for one of the objects, it may be
+ * rerun for that same object in the same pass.
+ */
+ int (*process_obj)(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj);
+};
+
+/**
+ * struct i915_gem_apply_to_region - Argument to the struct
+ * i915_gem_apply_to_region_ops functions.
+ * @ops: The ops for the operation.
+ * @ww: Locking context used for the transaction.
+ * @interruptible: Whether to perform object locking interruptible.
+ *
+ * This structure is intended to be embedded in a private struct if needed
+ */
+struct i915_gem_apply_to_region {
+ const struct i915_gem_apply_to_region_ops *ops;
+ struct i915_gem_ww_ctx *ww;
+ u32 interruptible:1;
+};
+
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
@@ -22,4 +57,6 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
resource_size_t page_size,
unsigned int flags);
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 2/6] drm/i915/gem: Implement a function to process all gem objects of a region
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
An upcoming common pattern is to traverse the region object list and
perform certain actions on all objects in a region. It's a little tricky
to get the list locking right, in particular since a gem object may
change region unless it's pinned or the object lock is held.
Define a function that does this for us and that takes an argument that
defines the action to be performed on each object.
v3:
- Improve structure documentation a bit (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++++++++++
2 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 1f557b2178ed..a016ccec36f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -80,3 +80,73 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
i915_gem_object_free(obj);
return ERR_PTR(err);
}
+
+/**
+ * i915_gem_process_region - Iterate over all objects of a region using ops
+ * to process and optionally skip objects
+ * @mr: The memory region
+ * @apply: ops and private data
+ *
+ * This function can be used to iterate over the regions object list,
+ * checking whether to skip objects, and, if not, lock the objects and
+ * process them using the supplied ops. Note that this function temporarily
+ * removes objects from the region list while iterating, so that if run
+ * concurrently with itself may not iterate over all objects.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply)
+{
+ const struct i915_gem_apply_to_region_ops *ops = apply->ops;
+ struct drm_i915_gem_object *obj;
+ struct list_head still_in_list;
+ int ret = 0;
+
+ /*
+ * In the future, a non-NULL apply->ww could mean the caller is
+ * already in a locking transaction and provides its own context.
+ */
+ GEM_WARN_ON(apply->ww);
+
+ INIT_LIST_HEAD(&still_in_list);
+ mutex_lock(&mr->objects.lock);
+ for (;;) {
+ struct i915_gem_ww_ctx ww;
+
+ obj = list_first_entry_or_null(&mr->objects.list, typeof(*obj),
+ mm.region_link);
+ if (!obj)
+ break;
+
+ list_move_tail(&obj->mm.region_link, &still_in_list);
+ if (!kref_get_unless_zero(&obj->base.refcount))
+ continue;
+
+ /*
+ * Note: Someone else might be migrating the object at this
+ * point. The object's region is not stable until we lock
+ * the object.
+ */
+ mutex_unlock(&mr->objects.lock);
+ apply->ww = &ww;
+ for_i915_gem_ww(&ww, ret, apply->interruptible) {
+ ret = i915_gem_object_lock(obj, apply->ww);
+ if (ret)
+ continue;
+
+ if (obj->mm.region == mr)
+ ret = ops->process_obj(apply, obj);
+ /* Implicit object unlock */
+ }
+
+ i915_gem_object_put(obj);
+ mutex_lock(&mr->objects.lock);
+ if (ret)
+ break;
+ }
+ list_splice_tail(&still_in_list, &mr->objects.list);
+ mutex_unlock(&mr->objects.lock);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index 1008e580a89a..fcaa12d657d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -12,6 +12,41 @@ struct intel_memory_region;
struct drm_i915_gem_object;
struct sg_table;
+struct i915_gem_apply_to_region;
+
+/**
+ * struct i915_gem_apply_to_region_ops - ops to use when iterating over all
+ * region objects.
+ */
+struct i915_gem_apply_to_region_ops {
+ /**
+ * process_obj - Process the current object
+ * @apply: Embed this for private data.
+ * @obj: The current object.
+ *
+ * Note that if this function is part of a ww transaction, and
+ * if returns -EDEADLK for one of the objects, it may be
+ * rerun for that same object in the same pass.
+ */
+ int (*process_obj)(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj);
+};
+
+/**
+ * struct i915_gem_apply_to_region - Argument to the struct
+ * i915_gem_apply_to_region_ops functions.
+ * @ops: The ops for the operation.
+ * @ww: Locking context used for the transaction.
+ * @interruptible: Whether to perform object locking interruptible.
+ *
+ * This structure is intended to be embedded in a private struct if needed
+ */
+struct i915_gem_apply_to_region {
+ const struct i915_gem_apply_to_region_ops *ops;
+ struct i915_gem_ww_ctx *ww;
+ u32 interruptible:1;
+};
+
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
@@ -22,4 +57,6 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
resource_size_t page_size,
unsigned int flags);
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 2/6] drm/i915/gem: Implement a function to process all gem objects of a region
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-16 10:23 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-16 10:23 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> An upcoming common pattern is to traverse the region object list and
> perform certain actions on all objects in a region. It's a little tricky
> to get the list locking right, in particular since a gem object may
> change region unless it's pinned or the object lock is held.
>
> Define a function that does this for us and that takes an argument that
> defines the action to be performed on each object.
>
> v3:
> - Improve structure documentation a bit (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/gem: Implement a function to process all gem objects of a region
@ 2021-09-16 10:23 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-16 10:23 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> An upcoming common pattern is to traverse the region object list and
> perform certain actions on all objects in a region. It's a little tricky
> to get the list locking right, in particular since a gem object may
> change region unless it's pinned or the object lock is held.
>
> Define a function that does this for us and that takes an argument that
> defines the action to be performed on each object.
>
> v3:
> - Improve structure documentation a bit (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Just evict unpinned objects to system. For pinned LMEM objects,
make a backup system object and blit the contents to that.
Backup is performed in three steps,
1: Opportunistically evict evictable objects using the gpu blitter.
2: After gt idle, evict evictable objects using the gpu blitter. This will
be modified in an upcoming patch to backup pinned objects that are not used
by the blitter itself.
3: Backup remaining pinned objects using memcpy.
Also move uC suspend to after 2) to make sure we have a functional GuC
during 2) if using GuC submission.
v2:
- Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
suspend / resume works with a slightly modified GuC submission enabling
patch series.
v3:
- Fix a potential use-after-free (Matthew Auld)
- Use i915_gem_object_create_shmem() instead of
i915_gem_object_create_region (Matthew Auld)
- Minor simplifications (Matthew Auld)
- Fix up kerneldoc for i195_ttm_restore_region().
- Final lmem_suspend() call moved to i915_gem_backup_suspend from
i915_gem_suspend_late, since the latter gets called at driver unload
and we don't unnecessarily want to run it at that time.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 92 +++++++-
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++-
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 203 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 24 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
11 files changed, 362 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d371be7dc5c..f9b69492a56c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -154,6 +154,7 @@ gem-y += \
gem/i915_gem_throttle.o \
gem/i915_gem_tiling.o \
gem/i915_gem_ttm.o \
+ gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2471f36aaff3..734cc8e16481 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -534,6 +534,7 @@ struct drm_i915_gem_object {
struct {
struct sg_table *cached_io_st;
struct i915_gem_object_page_iter get_io_page;
+ struct drm_i915_gem_object *backup;
bool created:1;
} ttm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8b9d7d14c4bd..8736ae1dfbb2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -5,6 +5,7 @@
*/
#include "gem/i915_gem_pm.h"
+#include "gem/i915_gem_ttm_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
@@ -39,7 +40,86 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
}
-void i915_gem_suspend_late(struct drm_i915_private *i915)
+static int lmem_restore(struct drm_i915_private *i915, bool allow_gpu)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_restore_region(mr, allow_gpu);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int lmem_suspend(struct drm_i915_private *i915, bool allow_gpu,
+ bool backup_pinned)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_backup_region(mr, allow_gpu, backup_pinned);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void lmem_recover(struct drm_i915_private *i915)
+{
+ struct intel_memory_region *mr;
+ int id;
+
+ for_each_memory_region(mr, i915, id)
+ if (mr->type == INTEL_MEMORY_LOCAL)
+ i915_ttm_recover_region(mr);
+}
+
+int i915_gem_backup_suspend(struct drm_i915_private *i915)
+{
+ int ret;
+
+ /* Opportunistically try to evict unpinned objects */
+ ret = lmem_suspend(i915, true, false);
+ if (ret)
+ goto out_recover;
+
+ i915_gem_suspend(i915);
+
+ /*
+ * More objects may have become unpinned as requests were
+ * retired. Now try to evict again. The gt may be wedged here
+ * in which case we automatically fall back to memcpy.
+ */
+ ret = lmem_suspend(i915, true, false);
+ if (ret)
+ goto out_recover;
+
+ /*
+ * Remaining objects are backed up using memcpy once we've stopped
+ * using the migrate context.
+ */
+ ret = lmem_suspend(i915, false, true);
+ if (ret)
+ goto out_recover;
+
+ return 0;
+
+out_recover:
+ lmem_recover(i915);
+
+ return ret;
+}
+
+int i915_gem_suspend_late(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
struct list_head *phases[] = {
@@ -83,6 +163,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
if (flush)
wbinvd_on_all_cpus();
+
+ return 0;
}
int i915_gem_freeze(struct drm_i915_private *i915)
@@ -128,12 +210,20 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ int ret;
+
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
+ ret = lmem_restore(i915, false);
+ GEM_WARN_ON(ret);
+
/*
* As we didn't flush the kernel context before suspend, we cannot
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
intel_gt_resume(&i915->gt);
+
+ ret = lmem_restore(i915, true);
+ GEM_WARN_ON(ret);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index c9a66630e92e..1b37d2bb6de8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -17,7 +17,8 @@ void i915_gem_resume(struct drm_i915_private *i915);
void i915_gem_idle_work_handler(struct work_struct *work);
void i915_gem_suspend(struct drm_i915_private *i915);
-void i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_backup_suspend(struct drm_i915_private *i915);
int i915_gem_freeze(struct drm_i915_private *i915);
int i915_gem_freeze_late(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index a75bb94d029b..91fe24bb41c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -10,18 +10,16 @@
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
+#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_object.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
-#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_ttm_pm.h"
-#include "gt/intel_migrate.h"
-#include "gt/intel_engine_pm.h"
-#define I915_PL_LMEM0 TTM_PL_PRIV
-#define I915_PL_SYSTEM TTM_PL_SYSTEM
-#define I915_PL_STOLEN TTM_PL_VRAM
-#define I915_PL_GGTT TTM_PL_TT
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_migrate.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -64,6 +62,20 @@ static struct ttm_placement i915_sys_placement = {
.busy_placement = &sys_placement_flags,
};
+/**
+ * i915_ttm_sys_placement - Return the struct ttm_placement to be
+ * used for an object in system memory.
+ *
+ * Rather than making the struct extern, use this
+ * function.
+ *
+ * Return: A pointer to a static variable for sys placement.
+ */
+struct ttm_placement *i915_ttm_sys_placement(void)
+{
+ return &i915_sys_placement;
+}
+
static int i915_ttm_err_to_gem(int err)
{
/* Fastpath */
@@ -445,7 +457,7 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
enum i915_cache_level src_level, dst_level;
int ret;
- if (!i915->gt.migrate.context)
+ if (!i915->gt.migrate.context || intel_gt_is_wedged(&i915->gt))
return -EINVAL;
dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
@@ -889,6 +901,7 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ i915_ttm_backup_free(obj);
i915_gem_object_release_memory_region(obj);
mutex_destroy(&obj->ttm.get_io_page.lock);
if (obj->ttm.created)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 34ac78d47b0d..0b7291dd897c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -50,4 +50,14 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
struct drm_i915_gem_object *src,
bool allow_accel, bool intr);
+
+/* Internal I915 TTM declarations and definitions below. */
+
+#define I915_PL_LMEM0 TTM_PL_PRIV
+#define I915_PL_SYSTEM TTM_PL_SYSTEM
+#define I915_PL_STOLEN TTM_PL_VRAM
+#define I915_PL_GGTT TTM_PL_TT
+
+struct ttm_placement *i915_ttm_sys_placement(void);
+
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
new file mode 100644
index 000000000000..30c13cfe851c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_tt.h>
+
+#include "i915_drv.h"
+#include "intel_memory_region.h"
+#include "intel_region_ttm.h"
+
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
+#include "gem/i915_gem_ttm_pm.h"
+
+/**
+ * i915_ttm_backup_free - Free any backup attached to this object
+ * @obj: The object whose backup is to be freed.
+ */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj)
+{
+ if (obj->ttm.backup) {
+ i915_gem_object_put(obj->ttm.backup);
+ obj->ttm.backup = NULL;
+ }
+}
+
+/**
+ * struct i915_gem_ttm_pm_apply - Apply-to-region subclass for restore
+ * @base: The i915_gem_apply_to_region we derive from.
+ * @allow_gpu: Whether using the gpu blitter is allowed.
+ * @backup_pinned: On backup, backup also pinned objects.
+ */
+struct i915_gem_ttm_pm_apply {
+ struct i915_gem_apply_to_region base;
+ bool allow_gpu : 1;
+ bool backup_pinned : 1;
+};
+
+static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct ttm_buffer_object *backup_bo;
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
+ struct drm_i915_gem_object *backup;
+ struct ttm_operation_ctx ctx = {};
+ int err = 0;
+
+ if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
+ return 0;
+
+ if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
+ return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
+
+ if (!pm_apply->backup_pinned)
+ return 0;
+
+ backup = i915_gem_object_create_shmem(i915, obj->base.size);
+ if (IS_ERR(backup))
+ return PTR_ERR(backup);
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ goto out_no_lock;
+
+ backup_bo = i915_gem_to_ttm(backup);
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (err)
+ goto out_no_populate;
+
+ err = i915_gem_obj_copy_ttm(backup, obj, pm_apply->allow_gpu, false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = backup;
+ return 0;
+
+out_no_populate:
+ i915_gem_ww_unlock_single(backup);
+out_no_lock:
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+static int i915_ttm_recover(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ i915_ttm_backup_free(obj);
+ return 0;
+}
+
+/**
+ * i915_ttm_recover_region - Free the backup of all objects of a region
+ * @mr: The memory region
+ *
+ * Checks all objects of a region if there is backup attached and if so
+ * frees that backup. Typically this is called to recover after a partially
+ * performed backup.
+ */
+void i915_ttm_recover_region(struct intel_memory_region *mr)
+{
+ static const struct i915_gem_apply_to_region_ops recover_ops = {
+ .process_obj = i915_ttm_recover,
+ };
+ struct i915_gem_apply_to_region apply = {.ops = &recover_ops};
+ int ret;
+
+ ret = i915_gem_process_region(mr, &apply);
+ GEM_WARN_ON(ret);
+}
+
+/**
+ * i915_ttm_backup_region - Back up all objects of a region to smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter for this backup.
+ * @backup_pinned: Backup also pinned objects.
+ *
+ * Loops over all objects of a region and either evicts them if they are
+ * evictable or backs them up using a backup object if they are pinned.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_backup_region(struct intel_memory_region *mr, bool allow_gpu,
+ bool backup_pinned)
+{
+ static const struct i915_gem_apply_to_region_ops backup_ops = {
+ .process_obj = i915_ttm_backup,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &backup_ops},
+ .allow_gpu = allow_gpu,
+ .backup_pinned = backup_pinned,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
+
+static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct drm_i915_gem_object *backup = obj->ttm.backup;
+ struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
+ struct ttm_operation_ctx ctx = {};
+ int err;
+
+ if (!backup)
+ return 0;
+
+ if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ return 0;
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ return err;
+
+ /* Content may have been swapped. */
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (!err) {
+ err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
+ false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = NULL;
+ err = 0;
+ }
+
+ i915_gem_ww_unlock_single(backup);
+
+ if (!err)
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+/**
+ * i915_ttm_restore_region - Restore backed-up objects of a region from smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter to recover.
+ *
+ * Loops over all objects of a region and if they are backed-up, restores
+ * them from smem.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_restore_region(struct intel_memory_region *mr, bool allow_gpu)
+{
+ static const struct i915_gem_apply_to_region_ops restore_ops = {
+ .process_obj = i915_ttm_restore,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &restore_ops},
+ .allow_gpu = allow_gpu,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
new file mode 100644
index 000000000000..4da27c21f3f4
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _I915_GEM_TTM_PM_H_
+#define _I915_GEM_TTM_PM_H_
+
+#include <linux/types.h>
+
+struct intel_memory_region;
+struct drm_i915_gem_object;
+
+int i915_ttm_backup_region(struct intel_memory_region *mr, bool allow_gpu,
+ bool backup_pinned);
+
+void i915_ttm_recover_region(struct intel_memory_region *mr);
+
+int i915_ttm_restore_region(struct intel_memory_region *mr, bool allow_gpu);
+
+/* Internal I915 TTM functions below. */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index dea8e2479897..c8e439d3b0e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -295,8 +295,6 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
{
user_forcewake(gt, true);
wait_for_suspend(gt);
-
- intel_uc_suspend(>->uc);
}
static suspend_state_t pm_suspend_target(void)
@@ -320,6 +318,8 @@ void intel_gt_suspend_late(struct intel_gt *gt)
GEM_BUG_ON(gt->awake);
+ intel_uc_suspend(>->uc);
+
/*
* On disabling the device, we want to turn off HW access to memory
* that we no longer own.
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59fb4c710c8c..ffb54ea26dcc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1096,9 +1096,7 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- i915_gem_suspend(i915);
-
- return 0;
+ return i915_gem_backup_suspend(i915);
}
static int i915_drm_suspend(struct drm_device *dev)
@@ -1167,7 +1165,11 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
disable_rpm_wakeref_asserts(rpm);
- i915_gem_suspend_late(dev_priv);
+ ret = i915_gem_suspend_late(dev_priv);
+ if (ret) {
+ enable_rpm_wakeref_asserts(rpm);
+ return ret;
+ }
intel_uncore_suspend(&dev_priv->uncore);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37c1ca266bcd..757e7e065179 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1841,7 +1841,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915);
void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
void i915_gem_driver_release(struct drm_i915_private *dev_priv);
void i915_gem_suspend(struct drm_i915_private *dev_priv);
-void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
+int i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Just evict unpinned objects to system. For pinned LMEM objects,
make a backup system object and blit the contents to that.
Backup is performed in three steps,
1: Opportunistically evict evictable objects using the gpu blitter.
2: After gt idle, evict evictable objects using the gpu blitter. This will
be modified in an upcoming patch to backup pinned objects that are not used
by the blitter itself.
3: Backup remaining pinned objects using memcpy.
Also move uC suspend to after 2) to make sure we have a functional GuC
during 2) if using GuC submission.
v2:
- Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
suspend / resume works with a slightly modified GuC submission enabling
patch series.
v3:
- Fix a potential use-after-free (Matthew Auld)
- Use i915_gem_object_create_shmem() instead of
i915_gem_object_create_region (Matthew Auld)
- Minor simplifications (Matthew Auld)
- Fix up kerneldoc for i195_ttm_restore_region().
- Final lmem_suspend() call moved to i915_gem_backup_suspend from
i915_gem_suspend_late, since the latter gets called at driver unload
and we don't unnecessarily want to run it at that time.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 92 +++++++-
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++-
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 203 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 24 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
11 files changed, 362 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d371be7dc5c..f9b69492a56c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -154,6 +154,7 @@ gem-y += \
gem/i915_gem_throttle.o \
gem/i915_gem_tiling.o \
gem/i915_gem_ttm.o \
+ gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2471f36aaff3..734cc8e16481 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -534,6 +534,7 @@ struct drm_i915_gem_object {
struct {
struct sg_table *cached_io_st;
struct i915_gem_object_page_iter get_io_page;
+ struct drm_i915_gem_object *backup;
bool created:1;
} ttm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8b9d7d14c4bd..8736ae1dfbb2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -5,6 +5,7 @@
*/
#include "gem/i915_gem_pm.h"
+#include "gem/i915_gem_ttm_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
@@ -39,7 +40,86 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
}
-void i915_gem_suspend_late(struct drm_i915_private *i915)
+static int lmem_restore(struct drm_i915_private *i915, bool allow_gpu)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_restore_region(mr, allow_gpu);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int lmem_suspend(struct drm_i915_private *i915, bool allow_gpu,
+ bool backup_pinned)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_backup_region(mr, allow_gpu, backup_pinned);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void lmem_recover(struct drm_i915_private *i915)
+{
+ struct intel_memory_region *mr;
+ int id;
+
+ for_each_memory_region(mr, i915, id)
+ if (mr->type == INTEL_MEMORY_LOCAL)
+ i915_ttm_recover_region(mr);
+}
+
+int i915_gem_backup_suspend(struct drm_i915_private *i915)
+{
+ int ret;
+
+ /* Opportunistically try to evict unpinned objects */
+ ret = lmem_suspend(i915, true, false);
+ if (ret)
+ goto out_recover;
+
+ i915_gem_suspend(i915);
+
+ /*
+ * More objects may have become unpinned as requests were
+ * retired. Now try to evict again. The gt may be wedged here
+ * in which case we automatically fall back to memcpy.
+ */
+ ret = lmem_suspend(i915, true, false);
+ if (ret)
+ goto out_recover;
+
+ /*
+ * Remaining objects are backed up using memcpy once we've stopped
+ * using the migrate context.
+ */
+ ret = lmem_suspend(i915, false, true);
+ if (ret)
+ goto out_recover;
+
+ return 0;
+
+out_recover:
+ lmem_recover(i915);
+
+ return ret;
+}
+
+int i915_gem_suspend_late(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
struct list_head *phases[] = {
@@ -83,6 +163,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
if (flush)
wbinvd_on_all_cpus();
+
+ return 0;
}
int i915_gem_freeze(struct drm_i915_private *i915)
@@ -128,12 +210,20 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ int ret;
+
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
+ ret = lmem_restore(i915, false);
+ GEM_WARN_ON(ret);
+
/*
* As we didn't flush the kernel context before suspend, we cannot
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
intel_gt_resume(&i915->gt);
+
+ ret = lmem_restore(i915, true);
+ GEM_WARN_ON(ret);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index c9a66630e92e..1b37d2bb6de8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -17,7 +17,8 @@ void i915_gem_resume(struct drm_i915_private *i915);
void i915_gem_idle_work_handler(struct work_struct *work);
void i915_gem_suspend(struct drm_i915_private *i915);
-void i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_backup_suspend(struct drm_i915_private *i915);
int i915_gem_freeze(struct drm_i915_private *i915);
int i915_gem_freeze_late(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index a75bb94d029b..91fe24bb41c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -10,18 +10,16 @@
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
+#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_object.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
-#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_ttm_pm.h"
-#include "gt/intel_migrate.h"
-#include "gt/intel_engine_pm.h"
-#define I915_PL_LMEM0 TTM_PL_PRIV
-#define I915_PL_SYSTEM TTM_PL_SYSTEM
-#define I915_PL_STOLEN TTM_PL_VRAM
-#define I915_PL_GGTT TTM_PL_TT
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_migrate.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -64,6 +62,20 @@ static struct ttm_placement i915_sys_placement = {
.busy_placement = &sys_placement_flags,
};
+/**
+ * i915_ttm_sys_placement - Return the struct ttm_placement to be
+ * used for an object in system memory.
+ *
+ * Rather than making the struct extern, use this
+ * function.
+ *
+ * Return: A pointer to a static variable for sys placement.
+ */
+struct ttm_placement *i915_ttm_sys_placement(void)
+{
+ return &i915_sys_placement;
+}
+
static int i915_ttm_err_to_gem(int err)
{
/* Fastpath */
@@ -445,7 +457,7 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
enum i915_cache_level src_level, dst_level;
int ret;
- if (!i915->gt.migrate.context)
+ if (!i915->gt.migrate.context || intel_gt_is_wedged(&i915->gt))
return -EINVAL;
dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
@@ -889,6 +901,7 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ i915_ttm_backup_free(obj);
i915_gem_object_release_memory_region(obj);
mutex_destroy(&obj->ttm.get_io_page.lock);
if (obj->ttm.created)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 34ac78d47b0d..0b7291dd897c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -50,4 +50,14 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
struct drm_i915_gem_object *src,
bool allow_accel, bool intr);
+
+/* Internal I915 TTM declarations and definitions below. */
+
+#define I915_PL_LMEM0 TTM_PL_PRIV
+#define I915_PL_SYSTEM TTM_PL_SYSTEM
+#define I915_PL_STOLEN TTM_PL_VRAM
+#define I915_PL_GGTT TTM_PL_TT
+
+struct ttm_placement *i915_ttm_sys_placement(void);
+
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
new file mode 100644
index 000000000000..30c13cfe851c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_tt.h>
+
+#include "i915_drv.h"
+#include "intel_memory_region.h"
+#include "intel_region_ttm.h"
+
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
+#include "gem/i915_gem_ttm_pm.h"
+
+/**
+ * i915_ttm_backup_free - Free any backup attached to this object
+ * @obj: The object whose backup is to be freed.
+ */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj)
+{
+ if (obj->ttm.backup) {
+ i915_gem_object_put(obj->ttm.backup);
+ obj->ttm.backup = NULL;
+ }
+}
+
+/**
+ * struct i915_gem_ttm_pm_apply - Apply-to-region subclass for restore
+ * @base: The i915_gem_apply_to_region we derive from.
+ * @allow_gpu: Whether using the gpu blitter is allowed.
+ * @backup_pinned: On backup, backup also pinned objects.
+ */
+struct i915_gem_ttm_pm_apply {
+ struct i915_gem_apply_to_region base;
+ bool allow_gpu : 1;
+ bool backup_pinned : 1;
+};
+
+static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct ttm_buffer_object *backup_bo;
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
+ struct drm_i915_gem_object *backup;
+ struct ttm_operation_ctx ctx = {};
+ int err = 0;
+
+ if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
+ return 0;
+
+ if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
+ return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
+
+ if (!pm_apply->backup_pinned)
+ return 0;
+
+ backup = i915_gem_object_create_shmem(i915, obj->base.size);
+ if (IS_ERR(backup))
+ return PTR_ERR(backup);
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ goto out_no_lock;
+
+ backup_bo = i915_gem_to_ttm(backup);
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (err)
+ goto out_no_populate;
+
+ err = i915_gem_obj_copy_ttm(backup, obj, pm_apply->allow_gpu, false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = backup;
+ return 0;
+
+out_no_populate:
+ i915_gem_ww_unlock_single(backup);
+out_no_lock:
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+static int i915_ttm_recover(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ i915_ttm_backup_free(obj);
+ return 0;
+}
+
+/**
+ * i915_ttm_recover_region - Free the backup of all objects of a region
+ * @mr: The memory region
+ *
+ * Checks all objects of a region if there is backup attached and if so
+ * frees that backup. Typically this is called to recover after a partially
+ * performed backup.
+ */
+void i915_ttm_recover_region(struct intel_memory_region *mr)
+{
+ static const struct i915_gem_apply_to_region_ops recover_ops = {
+ .process_obj = i915_ttm_recover,
+ };
+ struct i915_gem_apply_to_region apply = {.ops = &recover_ops};
+ int ret;
+
+ ret = i915_gem_process_region(mr, &apply);
+ GEM_WARN_ON(ret);
+}
+
+/**
+ * i915_ttm_backup_region - Back up all objects of a region to smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter for this backup.
+ * @backup_pinned: Backup also pinned objects.
+ *
+ * Loops over all objects of a region and either evicts them if they are
+ * evictable or backs them up using a backup object if they are pinned.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_backup_region(struct intel_memory_region *mr, bool allow_gpu,
+ bool backup_pinned)
+{
+ static const struct i915_gem_apply_to_region_ops backup_ops = {
+ .process_obj = i915_ttm_backup,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &backup_ops},
+ .allow_gpu = allow_gpu,
+ .backup_pinned = backup_pinned,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
+
+static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct drm_i915_gem_object *backup = obj->ttm.backup;
+ struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
+ struct ttm_operation_ctx ctx = {};
+ int err;
+
+ if (!backup)
+ return 0;
+
+ if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ return 0;
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ return err;
+
+ /* Content may have been swapped. */
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (!err) {
+ err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
+ false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = NULL;
+ err = 0;
+ }
+
+ i915_gem_ww_unlock_single(backup);
+
+ if (!err)
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+/**
+ * i915_ttm_restore_region - Restore backed-up objects of a region from smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter to recover.
+ *
+ * Loops over all objects of a region and if they are backed-up, restores
+ * them from smem.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_restore_region(struct intel_memory_region *mr, bool allow_gpu)
+{
+ static const struct i915_gem_apply_to_region_ops restore_ops = {
+ .process_obj = i915_ttm_restore,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &restore_ops},
+ .allow_gpu = allow_gpu,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
new file mode 100644
index 000000000000..4da27c21f3f4
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _I915_GEM_TTM_PM_H_
+#define _I915_GEM_TTM_PM_H_
+
+#include <linux/types.h>
+
+struct intel_memory_region;
+struct drm_i915_gem_object;
+
+int i915_ttm_backup_region(struct intel_memory_region *mr, bool allow_gpu,
+ bool backup_pinned);
+
+void i915_ttm_recover_region(struct intel_memory_region *mr);
+
+int i915_ttm_restore_region(struct intel_memory_region *mr, bool allow_gpu);
+
+/* Internal I915 TTM functions below. */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index dea8e2479897..c8e439d3b0e3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -295,8 +295,6 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
{
user_forcewake(gt, true);
wait_for_suspend(gt);
-
- intel_uc_suspend(>->uc);
}
static suspend_state_t pm_suspend_target(void)
@@ -320,6 +318,8 @@ void intel_gt_suspend_late(struct intel_gt *gt)
GEM_BUG_ON(gt->awake);
+ intel_uc_suspend(>->uc);
+
/*
* On disabling the device, we want to turn off HW access to memory
* that we no longer own.
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 59fb4c710c8c..ffb54ea26dcc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1096,9 +1096,7 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- i915_gem_suspend(i915);
-
- return 0;
+ return i915_gem_backup_suspend(i915);
}
static int i915_drm_suspend(struct drm_device *dev)
@@ -1167,7 +1165,11 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
disable_rpm_wakeref_asserts(rpm);
- i915_gem_suspend_late(dev_priv);
+ ret = i915_gem_suspend_late(dev_priv);
+ if (ret) {
+ enable_rpm_wakeref_asserts(rpm);
+ return ret;
+ }
intel_uncore_suspend(&dev_priv->uncore);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37c1ca266bcd..757e7e065179 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1841,7 +1841,7 @@ void i915_gem_driver_unregister(struct drm_i915_private *i915);
void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
void i915_gem_driver_release(struct drm_i915_private *dev_priv);
void i915_gem_suspend(struct drm_i915_private *dev_priv);
-void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
+int i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-17 12:03 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-17 12:03 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Just evict unpinned objects to system. For pinned LMEM objects,
> make a backup system object and blit the contents to that.
>
> Backup is performed in three steps,
> 1: Opportunistically evict evictable objects using the gpu blitter.
> 2: After gt idle, evict evictable objects using the gpu blitter. This will
> be modified in an upcoming patch to backup pinned objects that are not used
> by the blitter itself.
> 3: Backup remaining pinned objects using memcpy.
>
> Also move uC suspend to after 2) to make sure we have a functional GuC
> during 2) if using GuC submission.
>
> v2:
> - Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
> suspend / resume works with a slightly modified GuC submission enabling
> patch series.
>
> v3:
> - Fix a potential use-after-free (Matthew Auld)
> - Use i915_gem_object_create_shmem() instead of
> i915_gem_object_create_region (Matthew Auld)
> - Minor simplifications (Matthew Auld)
> - Fix up kerneldoc for i195_ttm_restore_region().
> - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> i915_gem_suspend_late, since the latter gets called at driver unload
> and we don't unnecessarily want to run it at that time.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 92 +++++++-
> drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 +-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 203 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 24 +++
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 10 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 11 files changed, 362 insertions(+), 17 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9d371be7dc5c..f9b69492a56c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -154,6 +154,7 @@ gem-y += \
> gem/i915_gem_throttle.o \
> gem/i915_gem_tiling.o \
> gem/i915_gem_ttm.o \
> + gem/i915_gem_ttm_pm.o \
> gem/i915_gem_userptr.o \
> gem/i915_gem_wait.o \
> gem/i915_gemfs.o
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 2471f36aaff3..734cc8e16481 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -534,6 +534,7 @@ struct drm_i915_gem_object {
> struct {
> struct sg_table *cached_io_st;
> struct i915_gem_object_page_iter get_io_page;
> + struct drm_i915_gem_object *backup;
> bool created:1;
> } ttm;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 8b9d7d14c4bd..8736ae1dfbb2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -5,6 +5,7 @@
> */
>
> #include "gem/i915_gem_pm.h"
> +#include "gem/i915_gem_ttm_pm.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_gt_requests.h"
> @@ -39,7 +40,86 @@ void i915_gem_suspend(struct drm_i915_private *i915)
> i915_gem_drain_freed_objects(i915);
> }
>
> -void i915_gem_suspend_late(struct drm_i915_private *i915)
> +static int lmem_restore(struct drm_i915_private *i915, bool allow_gpu)
> +{
> + struct intel_memory_region *mr;
> + int ret = 0, id;
> +
> + for_each_memory_region(mr, i915, id) {
> + if (mr->type == INTEL_MEMORY_LOCAL) {
> + ret = i915_ttm_restore_region(mr, allow_gpu);
> + if (ret)
> + break;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static int lmem_suspend(struct drm_i915_private *i915, bool allow_gpu,
> + bool backup_pinned)
> +{
> + struct intel_memory_region *mr;
> + int ret = 0, id;
> +
> + for_each_memory_region(mr, i915, id) {
> + if (mr->type == INTEL_MEMORY_LOCAL) {
> + ret = i915_ttm_backup_region(mr, allow_gpu, backup_pinned);
> + if (ret)
> + break;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static void lmem_recover(struct drm_i915_private *i915)
> +{
> + struct intel_memory_region *mr;
> + int id;
> +
> + for_each_memory_region(mr, i915, id)
> + if (mr->type == INTEL_MEMORY_LOCAL)
> + i915_ttm_recover_region(mr);
> +}
> +
> +int i915_gem_backup_suspend(struct drm_i915_private *i915)
> +{
> + int ret;
> +
> + /* Opportunistically try to evict unpinned objects */
> + ret = lmem_suspend(i915, true, false);
> + if (ret)
> + goto out_recover;
> +
> + i915_gem_suspend(i915);
> +
> + /*
> + * More objects may have become unpinned as requests were
> + * retired. Now try to evict again. The gt may be wedged here
> + * in which case we automatically fall back to memcpy.
> + */
> + ret = lmem_suspend(i915, true, false);
> + if (ret)
> + goto out_recover;
> +
> + /*
> + * Remaining objects are backed up using memcpy once we've stopped
> + * using the migrate context.
> + */
> + ret = lmem_suspend(i915, false, true);
> + if (ret)
> + goto out_recover;
> +
> + return 0;
> +
> +out_recover:
> + lmem_recover(i915);
> +
> + return ret;
> +}
> +
> +int i915_gem_suspend_late(struct drm_i915_private *i915)
> {
> struct drm_i915_gem_object *obj;
> struct list_head *phases[] = {
> @@ -83,6 +163,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
> spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
> if (flush)
> wbinvd_on_all_cpus();
> +
> + return 0;
We can drop this change now?
I guess only slight concern is all the GEM_WARN_ON() instead of proper
error handling in some places, but hopefully these should never be hit
in practice,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Intel-gfx] [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
@ 2021-09-17 12:03 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-17 12:03 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Just evict unpinned objects to system. For pinned LMEM objects,
> make a backup system object and blit the contents to that.
>
> Backup is performed in three steps,
> 1: Opportunistically evict evictable objects using the gpu blitter.
> 2: After gt idle, evict evictable objects using the gpu blitter. This will
> be modified in an upcoming patch to backup pinned objects that are not used
> by the blitter itself.
> 3: Backup remaining pinned objects using memcpy.
>
> Also move uC suspend to after 2) to make sure we have a functional GuC
> during 2) if using GuC submission.
>
> v2:
> - Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
> suspend / resume works with a slightly modified GuC submission enabling
> patch series.
>
> v3:
> - Fix a potential use-after-free (Matthew Auld)
> - Use i915_gem_object_create_shmem() instead of
> i915_gem_object_create_region (Matthew Auld)
> - Minor simplifications (Matthew Auld)
> - Fix up kerneldoc for i195_ttm_restore_region().
> - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> i915_gem_suspend_late, since the latter gets called at driver unload
> and we don't unnecessarily want to run it at that time.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 92 +++++++-
> drivers/gpu/drm/i915/gem/i915_gem_pm.h | 3 +-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 203 ++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 24 +++
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 10 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 11 files changed, 362 insertions(+), 17 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9d371be7dc5c..f9b69492a56c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -154,6 +154,7 @@ gem-y += \
> gem/i915_gem_throttle.o \
> gem/i915_gem_tiling.o \
> gem/i915_gem_ttm.o \
> + gem/i915_gem_ttm_pm.o \
> gem/i915_gem_userptr.o \
> gem/i915_gem_wait.o \
> gem/i915_gemfs.o
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 2471f36aaff3..734cc8e16481 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -534,6 +534,7 @@ struct drm_i915_gem_object {
> struct {
> struct sg_table *cached_io_st;
> struct i915_gem_object_page_iter get_io_page;
> + struct drm_i915_gem_object *backup;
> bool created:1;
> } ttm;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 8b9d7d14c4bd..8736ae1dfbb2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -5,6 +5,7 @@
> */
>
> #include "gem/i915_gem_pm.h"
> +#include "gem/i915_gem_ttm_pm.h"
> #include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_gt_requests.h"
> @@ -39,7 +40,86 @@ void i915_gem_suspend(struct drm_i915_private *i915)
> i915_gem_drain_freed_objects(i915);
> }
>
> -void i915_gem_suspend_late(struct drm_i915_private *i915)
> +static int lmem_restore(struct drm_i915_private *i915, bool allow_gpu)
> +{
> + struct intel_memory_region *mr;
> + int ret = 0, id;
> +
> + for_each_memory_region(mr, i915, id) {
> + if (mr->type == INTEL_MEMORY_LOCAL) {
> + ret = i915_ttm_restore_region(mr, allow_gpu);
> + if (ret)
> + break;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static int lmem_suspend(struct drm_i915_private *i915, bool allow_gpu,
> + bool backup_pinned)
> +{
> + struct intel_memory_region *mr;
> + int ret = 0, id;
> +
> + for_each_memory_region(mr, i915, id) {
> + if (mr->type == INTEL_MEMORY_LOCAL) {
> + ret = i915_ttm_backup_region(mr, allow_gpu, backup_pinned);
> + if (ret)
> + break;
> + }
> + }
> +
> + return ret;
> +}
> +
> +static void lmem_recover(struct drm_i915_private *i915)
> +{
> + struct intel_memory_region *mr;
> + int id;
> +
> + for_each_memory_region(mr, i915, id)
> + if (mr->type == INTEL_MEMORY_LOCAL)
> + i915_ttm_recover_region(mr);
> +}
> +
> +int i915_gem_backup_suspend(struct drm_i915_private *i915)
> +{
> + int ret;
> +
> + /* Opportunistically try to evict unpinned objects */
> + ret = lmem_suspend(i915, true, false);
> + if (ret)
> + goto out_recover;
> +
> + i915_gem_suspend(i915);
> +
> + /*
> + * More objects may have become unpinned as requests were
> + * retired. Now try to evict again. The gt may be wedged here
> + * in which case we automatically fall back to memcpy.
> + */
> + ret = lmem_suspend(i915, true, false);
> + if (ret)
> + goto out_recover;
> +
> + /*
> + * Remaining objects are backed up using memcpy once we've stopped
> + * using the migrate context.
> + */
> + ret = lmem_suspend(i915, false, true);
> + if (ret)
> + goto out_recover;
> +
> + return 0;
> +
> +out_recover:
> + lmem_recover(i915);
> +
> + return ret;
> +}
> +
> +int i915_gem_suspend_late(struct drm_i915_private *i915)
> {
> struct drm_i915_gem_object *obj;
> struct list_head *phases[] = {
> @@ -83,6 +163,8 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
> spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
> if (flush)
> wbinvd_on_all_cpus();
> +
> + return 0;
We can drop this change now?
I guess only slight concern is all the GEM_WARN_ON() instead of proper
error handling in some places, but hopefully these should never be hit
in practice,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-20 10:49 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 10:49 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Just evict unpinned objects to system. For pinned LMEM objects,
> make a backup system object and blit the contents to that.
>
> Backup is performed in three steps,
> 1: Opportunistically evict evictable objects using the gpu blitter.
> 2: After gt idle, evict evictable objects using the gpu blitter. This will
> be modified in an upcoming patch to backup pinned objects that are not used
> by the blitter itself.
> 3: Backup remaining pinned objects using memcpy.
>
> Also move uC suspend to after 2) to make sure we have a functional GuC
> during 2) if using GuC submission.
>
> v2:
> - Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
> suspend / resume works with a slightly modified GuC submission enabling
> patch series.
>
> v3:
> - Fix a potential use-after-free (Matthew Auld)
> - Use i915_gem_object_create_shmem() instead of
> i915_gem_object_create_region (Matthew Auld)
> - Minor simplifications (Matthew Auld)
> - Fix up kerneldoc for i195_ttm_restore_region().
> - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> i915_gem_suspend_late, since the latter gets called at driver unload
> and we don't unnecessarily want to run it at that time.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
<snip>
> +
> +static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> + struct drm_i915_gem_object *obj)
> +{
> + struct i915_gem_ttm_pm_apply *pm_apply =
> + container_of(apply, typeof(*pm_apply), base);
> + struct drm_i915_gem_object *backup = obj->ttm.backup;
> + struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
> + struct ttm_operation_ctx ctx = {};
> + int err;
> +
> + if (!backup)
> + return 0;
> +
> + if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + return 0;
Hmm, do we ever hit this? I would presume anything that userspace
directly allocated in lmem can be kicked out with ttm_bo_validate(sys)
i.e backup == NULL?
> +
> + err = i915_gem_object_lock(backup, apply->ww);
> + if (err)
> + return err;
> +
> + /* Content may have been swapped. */
> + err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
> + if (!err) {
> + err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
> + false);
> + GEM_WARN_ON(err);
> +
> + obj->ttm.backup = NULL;
> + err = 0;
> + }
> +
> + i915_gem_ww_unlock_single(backup);
> +
> + if (!err)
> + i915_gem_object_put(backup);
> +
> + return err;
> +}
> +
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Intel-gfx] [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
@ 2021-09-20 10:49 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 10:49 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Just evict unpinned objects to system. For pinned LMEM objects,
> make a backup system object and blit the contents to that.
>
> Backup is performed in three steps,
> 1: Opportunistically evict evictable objects using the gpu blitter.
> 2: After gt idle, evict evictable objects using the gpu blitter. This will
> be modified in an upcoming patch to backup pinned objects that are not used
> by the blitter itself.
> 3: Backup remaining pinned objects using memcpy.
>
> Also move uC suspend to after 2) to make sure we have a functional GuC
> during 2) if using GuC submission.
>
> v2:
> - Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
> suspend / resume works with a slightly modified GuC submission enabling
> patch series.
>
> v3:
> - Fix a potential use-after-free (Matthew Auld)
> - Use i915_gem_object_create_shmem() instead of
> i915_gem_object_create_region (Matthew Auld)
> - Minor simplifications (Matthew Auld)
> - Fix up kerneldoc for i195_ttm_restore_region().
> - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> i915_gem_suspend_late, since the latter gets called at driver unload
> and we don't unnecessarily want to run it at that time.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
<snip>
> +
> +static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> + struct drm_i915_gem_object *obj)
> +{
> + struct i915_gem_ttm_pm_apply *pm_apply =
> + container_of(apply, typeof(*pm_apply), base);
> + struct drm_i915_gem_object *backup = obj->ttm.backup;
> + struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
> + struct ttm_operation_ctx ctx = {};
> + int err;
> +
> + if (!backup)
> + return 0;
> +
> + if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + return 0;
Hmm, do we ever hit this? I would presume anything that userspace
directly allocated in lmem can be kicked out with ttm_bo_validate(sys)
i.e backup == NULL?
> +
> + err = i915_gem_object_lock(backup, apply->ww);
> + if (err)
> + return err;
> +
> + /* Content may have been swapped. */
> + err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
> + if (!err) {
> + err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
> + false);
> + GEM_WARN_ON(err);
> +
> + obj->ttm.backup = NULL;
> + err = 0;
> + }
> +
> + i915_gem_ww_unlock_single(backup);
> +
> + if (!err)
> + i915_gem_object_put(backup);
> +
> + return err;
> +}
> +
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
2021-09-20 10:49 ` [Intel-gfx] " Matthew Auld
@ 2021-09-20 11:05 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-20 11:05 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On Mon, 2021-09-20 at 11:49 +0100, Matthew Auld wrote:
> On 14/09/2021 20:31, Thomas Hellström wrote:
> > Just evict unpinned objects to system. For pinned LMEM objects,
> > make a backup system object and blit the contents to that.
> >
> > Backup is performed in three steps,
> > 1: Opportunistically evict evictable objects using the gpu blitter.
> > 2: After gt idle, evict evictable objects using the gpu blitter.
> > This will
> > be modified in an upcoming patch to backup pinned objects that are
> > not used
> > by the blitter itself.
> > 3: Backup remaining pinned objects using memcpy.
> >
> > Also move uC suspend to after 2) to make sure we have a functional
> > GuC
> > during 2) if using GuC submission.
> >
> > v2:
> > - Major refactor to make sure gem_exec_suspend@hang-SX subtests
> > work, and
> > suspend / resume works with a slightly modified GuC submission
> > enabling
> > patch series.
> >
> > v3:
> > - Fix a potential use-after-free (Matthew Auld)
> > - Use i915_gem_object_create_shmem() instead of
> > i915_gem_object_create_region (Matthew Auld)
> > - Minor simplifications (Matthew Auld)
> > - Fix up kerneldoc for i195_ttm_restore_region().
> > - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> > i915_gem_suspend_late, since the latter gets called at driver
> > unload
> > and we don't unnecessarily want to run it at that time.
> >
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>
> <snip>
>
> > +
> > +static int i915_ttm_restore(struct i915_gem_apply_to_region
> > *apply,
> > + struct drm_i915_gem_object *obj)
> > +{
> > + struct i915_gem_ttm_pm_apply *pm_apply =
> > + container_of(apply, typeof(*pm_apply), base);
> > + struct drm_i915_gem_object *backup = obj->ttm.backup;
> > + struct ttm_buffer_object *backup_bo =
> > i915_gem_to_ttm(backup);
> > + struct ttm_operation_ctx ctx = {};
> > + int err;
> > +
> > + if (!backup)
> > + return 0;
> > +
> > + if (!pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_USER))
> > + return 0;
>
> Hmm, do we ever hit this? I would presume anything that userspace
> directly allocated in lmem can be kicked out with
> ttm_bo_validate(sys)
> i.e backup == NULL?
At this point, (before patch 6/6) I think we might do. Typical
candidates are dma-buf objects that have become pinned on exporting,
and perhaps framebuffers that are pinned, not sure they are unpinned
before we back them up.
But it might be that we should remove this after patch 6/6 where we
require a special flag for early recovers using memcpy.
/Thomas
>
> > +
> > + err = i915_gem_object_lock(backup, apply->ww);
> > + if (err)
> > + return err;
> > +
> > + /* Content may have been swapped. */
> > + err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm,
> > &ctx);
> > + if (!err) {
> > + err = i915_gem_obj_copy_ttm(obj, backup, pm_apply-
> > >allow_gpu,
> > + false);
> > + GEM_WARN_ON(err);
> > +
> > + obj->ttm.backup = NULL;
> > + err = 0;
> > + }
> > +
> > + i915_gem_ww_unlock_single(backup);
> > +
> > + if (!err)
> > + i915_gem_object_put(backup);
> > +
> > + return err;
> > +}
> > +
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Intel-gfx] [PATCH v3 3/6] drm/i915 Implement LMEM backup and restore for suspend / resume
@ 2021-09-20 11:05 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-20 11:05 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On Mon, 2021-09-20 at 11:49 +0100, Matthew Auld wrote:
> On 14/09/2021 20:31, Thomas Hellström wrote:
> > Just evict unpinned objects to system. For pinned LMEM objects,
> > make a backup system object and blit the contents to that.
> >
> > Backup is performed in three steps,
> > 1: Opportunistically evict evictable objects using the gpu blitter.
> > 2: After gt idle, evict evictable objects using the gpu blitter.
> > This will
> > be modified in an upcoming patch to backup pinned objects that are
> > not used
> > by the blitter itself.
> > 3: Backup remaining pinned objects using memcpy.
> >
> > Also move uC suspend to after 2) to make sure we have a functional
> > GuC
> > during 2) if using GuC submission.
> >
> > v2:
> > - Major refactor to make sure gem_exec_suspend@hang-SX subtests
> > work, and
> > suspend / resume works with a slightly modified GuC submission
> > enabling
> > patch series.
> >
> > v3:
> > - Fix a potential use-after-free (Matthew Auld)
> > - Use i915_gem_object_create_shmem() instead of
> > i915_gem_object_create_region (Matthew Auld)
> > - Minor simplifications (Matthew Auld)
> > - Fix up kerneldoc for i195_ttm_restore_region().
> > - Final lmem_suspend() call moved to i915_gem_backup_suspend from
> > i915_gem_suspend_late, since the latter gets called at driver
> > unload
> > and we don't unnecessarily want to run it at that time.
> >
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>
> <snip>
>
> > +
> > +static int i915_ttm_restore(struct i915_gem_apply_to_region
> > *apply,
> > + struct drm_i915_gem_object *obj)
> > +{
> > + struct i915_gem_ttm_pm_apply *pm_apply =
> > + container_of(apply, typeof(*pm_apply), base);
> > + struct drm_i915_gem_object *backup = obj->ttm.backup;
> > + struct ttm_buffer_object *backup_bo =
> > i915_gem_to_ttm(backup);
> > + struct ttm_operation_ctx ctx = {};
> > + int err;
> > +
> > + if (!backup)
> > + return 0;
> > +
> > + if (!pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_USER))
> > + return 0;
>
> Hmm, do we ever hit this? I would presume anything that userspace
> directly allocated in lmem can be kicked out with
> ttm_bo_validate(sys)
> i.e backup == NULL?
At this point, (before patch 6/6) I think we might do. Typical
candidates are dma-buf objects that have become pinned on exporting,
and perhaps framebuffers that are pinned, not sure they are unpinned
before we back them up.
But it might be that we should remove this after patch 6/6 where we
require a special flag for early recovers using memcpy.
/Thomas
>
> > +
> > + err = i915_gem_object_lock(backup, apply->ww);
> > + if (err)
> > + return err;
> > +
> > + /* Content may have been swapped. */
> > + err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm,
> > &ctx);
> > + if (!err) {
> > + err = i915_gem_obj_copy_ttm(obj, backup, pm_apply-
> > >allow_gpu,
> > + false);
> > + GEM_WARN_ON(err);
> > +
> > + obj->ttm.backup = NULL;
> > + err = 0;
> > + }
> > +
> > + i915_gem_ww_unlock_single(backup);
> > +
> > + if (!err)
> > + i915_gem_object_put(backup);
> > +
> > + return err;
> > +}
> > +
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 4/6] drm/i915/gt: Register the migrate contexts with their engines
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström,
Tvrtko Ursulin, Brost Matthew, Chris Wilson
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at resume time to reset the pinned
contexts.
This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
but proper LMEM backup / restore is needed for full suspend functionality.
However, note that even with full LMEM backup / restore it may be
desirable to keep the reset since backing up the migrate context images
must happen using memcpy() after the migrate context has become inactive,
and for performance- and other reasons we want to avoid memcpy() from
LMEM.
Also traverse the list at guc_init_lrc_mapping() calling
guc_kernel_context_pin() for the pinned contexts, like is already done
for the kernel context.
v2:
- Don't reset the contexts on each __engine_unpark() but rather at
resume time (Chris Wilson).
v3:
- Reset contexts in the engine sanitize callback. (Chris Wilson)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Brost Matthew <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++++++
.../drm/i915/gt/intel_execlists_submission.c | 2 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++++++---
9 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 930569a1a01f..12252c411159 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -153,6 +153,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+ /**
+ * pinned_contexts_link: List link for the engine's pinned contexts.
+ * This is only used if this is a perma-pinned kernel context and
+ * the list is assumed to only be manipulated during driver load
+ * or unload time so no mutex protection currently.
+ */
+ struct list_head pinned_contexts_link;
+
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..c606a4714904 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -320,6 +320,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
@@ -875,6 +876,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine,
return ERR_PTR(err);
}
+ list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
+
/*
* Give our perma-pinned kernel timelines a separate lockdep class,
* so that we can use them from within the normal user timelines
@@ -897,6 +900,7 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce)
list_del(&ce->timeline->engine_link);
mutex_unlock(&hwsp->vm->mutex);
+ list_del(&ce->pinned_contexts_link);
intel_context_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..dacd62773735 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -298,6 +298,29 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
intel_engine_init_heartbeat(engine);
}
+/**
+ * intel_engine_reset_pinned_contexts - Reset the pinned contexts of
+ * an engine.
+ * @engine: The engine whose pinned contexts we want to reset.
+ *
+ * Typically the pinned context LMEM images lose or get their content
+ * corrupted on suspend. This function resets their images.
+ */
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link) {
+ /* kernel context gets reset at __engine_unpark() */
+ if (ce == engine->kernel_context)
+ continue;
+
+ dbg_poison_ce(ce);
+ ce->ops->reset(ce);
+ }
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_engine_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index 70ea46d6cfb0..8520c595f5e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -69,4 +69,6 @@ intel_engine_create_kernel_request(struct intel_engine_cs *engine)
void intel_engine_init__pm(struct intel_engine_cs *engine);
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);
+
#endif /* INTEL_ENGINE_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..5ae1207c363b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -307,6 +307,13 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
+ /**
+ * pinned_contexts_list: List of pinned contexts. This list is only
+ * assumed to be manipulated during driver load- or unload time and
+ * does therefore not have any additional protection.
+ */
+ struct list_head pinned_contexts_list;
+
intel_engine_mask_t saturated; /* submitting semaphores too late? */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 87c595e4efe2..7147fe80919e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2787,6 +2787,8 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void enable_error_interrupt(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3c65efcb7bed..593524195707 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -17,6 +17,7 @@
#include "intel_ring.h"
#include "shmem_utils.h"
#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
/* Rough estimate of the typical request size, performing a flush,
* set-context and then emitting the batch.
@@ -292,6 +293,8 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void reset_prepare(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 2c1af030310c..8b89215afe46 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -376,6 +376,8 @@ int mock_engine_init(struct intel_engine_cs *engine)
{
struct intel_context *ce;
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
+
engine->sched_engine = i915_sched_engine_create(ENGINE_MOCK);
if (!engine->sched_engine)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c7a41802b448..ba0de35f6323 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2477,6 +2477,8 @@ static void guc_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void setup_hwsp(struct intel_engine_cs *engine)
@@ -2552,9 +2554,13 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* and even it did this code would be run again.
*/
- for_each_engine(engine, gt, id)
- if (engine->kernel_context)
- guc_kernel_context_pin(guc, engine->kernel_context);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link)
+ guc_kernel_context_pin(guc, ce);
+ }
}
static void guc_release(struct intel_engine_cs *engine)
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 4/6] drm/i915/gt: Register the migrate contexts with their engines
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström,
Tvrtko Ursulin, Brost Matthew, Chris Wilson
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at resume time to reset the pinned
contexts.
This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
but proper LMEM backup / restore is needed for full suspend functionality.
However, note that even with full LMEM backup / restore it may be
desirable to keep the reset since backing up the migrate context images
must happen using memcpy() after the migrate context has become inactive,
and for performance- and other reasons we want to avoid memcpy() from
LMEM.
Also traverse the list at guc_init_lrc_mapping() calling
guc_kernel_context_pin() for the pinned contexts, like is already done
for the kernel context.
v2:
- Don't reset the contexts on each __engine_unpark() but rather at
resume time (Chris Wilson).
v3:
- Reset contexts in the engine sanitize callback. (Chris Wilson)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Brost Matthew <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++++++
.../drm/i915/gt/intel_execlists_submission.c | 2 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++++++---
9 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 930569a1a01f..12252c411159 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -153,6 +153,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+ /**
+ * pinned_contexts_link: List link for the engine's pinned contexts.
+ * This is only used if this is a perma-pinned kernel context and
+ * the list is assumed to only be manipulated during driver load
+ * or unload time so no mutex protection currently.
+ */
+ struct list_head pinned_contexts_link;
+
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..c606a4714904 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -320,6 +320,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
@@ -875,6 +876,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine,
return ERR_PTR(err);
}
+ list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
+
/*
* Give our perma-pinned kernel timelines a separate lockdep class,
* so that we can use them from within the normal user timelines
@@ -897,6 +900,7 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce)
list_del(&ce->timeline->engine_link);
mutex_unlock(&hwsp->vm->mutex);
+ list_del(&ce->pinned_contexts_link);
intel_context_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..dacd62773735 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -298,6 +298,29 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
intel_engine_init_heartbeat(engine);
}
+/**
+ * intel_engine_reset_pinned_contexts - Reset the pinned contexts of
+ * an engine.
+ * @engine: The engine whose pinned contexts we want to reset.
+ *
+ * Typically the pinned context LMEM images lose or get their content
+ * corrupted on suspend. This function resets their images.
+ */
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link) {
+ /* kernel context gets reset at __engine_unpark() */
+ if (ce == engine->kernel_context)
+ continue;
+
+ dbg_poison_ce(ce);
+ ce->ops->reset(ce);
+ }
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_engine_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index 70ea46d6cfb0..8520c595f5e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -69,4 +69,6 @@ intel_engine_create_kernel_request(struct intel_engine_cs *engine)
void intel_engine_init__pm(struct intel_engine_cs *engine);
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);
+
#endif /* INTEL_ENGINE_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..5ae1207c363b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -307,6 +307,13 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
+ /**
+ * pinned_contexts_list: List of pinned contexts. This list is only
+ * assumed to be manipulated during driver load- or unload time and
+ * does therefore not have any additional protection.
+ */
+ struct list_head pinned_contexts_list;
+
intel_engine_mask_t saturated; /* submitting semaphores too late? */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 87c595e4efe2..7147fe80919e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2787,6 +2787,8 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void enable_error_interrupt(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3c65efcb7bed..593524195707 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -17,6 +17,7 @@
#include "intel_ring.h"
#include "shmem_utils.h"
#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
/* Rough estimate of the typical request size, performing a flush,
* set-context and then emitting the batch.
@@ -292,6 +293,8 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void reset_prepare(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 2c1af030310c..8b89215afe46 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -376,6 +376,8 @@ int mock_engine_init(struct intel_engine_cs *engine)
{
struct intel_context *ce;
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
+
engine->sched_engine = i915_sched_engine_create(ENGINE_MOCK);
if (!engine->sched_engine)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c7a41802b448..ba0de35f6323 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2477,6 +2477,8 @@ static void guc_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void setup_hwsp(struct intel_engine_cs *engine)
@@ -2552,9 +2554,13 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* and even it did this code would be run again.
*/
- for_each_engine(engine, gt, id)
- if (engine->kernel_context)
- guc_kernel_context_pin(guc, engine->kernel_context);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link)
+ guc_kernel_context_pin(guc, ce);
+ }
}
static void guc_release(struct intel_engine_cs *engine)
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 4/6] drm/i915/gt: Register the migrate contexts with their engines
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-20 9:53 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 9:53 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, Tvrtko Ursulin, Brost Matthew, Chris Wilson
On 14/09/2021 20:31, Thomas Hellström wrote:
> Pinned contexts, like the migrate contexts need reset after resume
> since their context image may have been lost. Also the GuC needs to
> register pinned contexts.
>
> Add a list to struct intel_engine_cs where we add all pinned contexts on
> creation, and traverse that list at resume time to reset the pinned
> contexts.
>
> This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
> but proper LMEM backup / restore is needed for full suspend functionality.
> However, note that even with full LMEM backup / restore it may be
> desirable to keep the reset since backing up the migrate context images
> must happen using memcpy() after the migrate context has become inactive,
> and for performance- and other reasons we want to avoid memcpy() from
> LMEM.
>
> Also traverse the list at guc_init_lrc_mapping() calling
> guc_kernel_context_pin() for the pinned contexts, like is already done
> for the kernel context.
>
> v2:
> - Don't reset the contexts on each __engine_unpark() but rather at
> resume time (Chris Wilson).
> v3:
> - Reset contexts in the engine sanitize callback. (Chris Wilson)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Brost Matthew <matthew.brost@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/gt: Register the migrate contexts with their engines
@ 2021-09-20 9:53 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 9:53 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, Tvrtko Ursulin, Brost Matthew, Chris Wilson
On 14/09/2021 20:31, Thomas Hellström wrote:
> Pinned contexts, like the migrate contexts need reset after resume
> since their context image may have been lost. Also the GuC needs to
> register pinned contexts.
>
> Add a list to struct intel_engine_cs where we add all pinned contexts on
> creation, and traverse that list at resume time to reset the pinned
> contexts.
>
> This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
> but proper LMEM backup / restore is needed for full suspend functionality.
> However, note that even with full LMEM backup / restore it may be
> desirable to keep the reset since backing up the migrate context images
> must happen using memcpy() after the migrate context has become inactive,
> and for performance- and other reasons we want to avoid memcpy() from
> LMEM.
>
> Also traverse the list at guc_init_lrc_mapping() calling
> guc_kernel_context_pin() for the pinned contexts, like is already done
> for the kernel context.
>
> v2:
> - Don't reset the contexts on each __engine_unpark() but rather at
> resume time (Chris Wilson).
> v3:
> - Reset contexts in the engine sanitize callback. (Chris Wilson)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Brost Matthew <matthew.brost@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.
v3:
- Slight documentation clarification (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++-------
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..118691ce81d7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
unsigned long flags;
-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
-#define I915_BO_ALLOC_USER BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
+/* Object is allowed to lose its contents on suspend / resume, even if pinned */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 30c13cfe851c..a87419755d43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -60,6 +60,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (!pm_apply->backup_pinned)
return 0;
+ if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
+ return 0;
+
backup = i915_gem_object_create_shmem(i915, obj->base.size);
if (IS_ERR(backup))
return PTR_ERR(backup);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
- obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
+ obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.
v3:
- Slight documentation clarification (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++-------
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..118691ce81d7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
unsigned long flags;
-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
-#define I915_BO_ALLOC_USER BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
+/* Object is allowed to lose its contents on suspend / resume, even if pinned */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 30c13cfe851c..a87419755d43 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -60,6 +60,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (!pm_apply->backup_pinned)
return 0;
+ if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
+ return 0;
+
backup = i915_gem_object_create_shmem(i915, obj->base.size);
if (IS_ERR(backup))
return PTR_ERR(backup);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
- obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
+ obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-20 9:57 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 9:57 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Pinned context images are now reset during resume. Don't back them up,
> and assuming that rings can be assumed empty at suspend, don't back them
> up either.
>
> Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
> object is allowed to lose its content on suspend.
>
> v3:
> - Slight documentation clarification (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v3 5/6] drm/i915: Don't back up pinned LMEM context images and rings during suspend
@ 2021-09-20 9:57 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 9:57 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> Pinned context images are now reset during resume. Don't back them up,
> and assuming that rings can be assumed empty at suspend, don't back them
> up either.
>
> Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
> object is allowed to lose its content on suspend.
>
> v3:
> - Slight documentation clarification (Matthew Auld)
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-14 19:31 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
We really only need memcpy restore for objects that affect the
operability of the migrate context. That is, primarily the page-table
objects of the migrate VM.
Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
restores using memcpy and a way to assign LMEM page-table object flags
to be used by the vms.
Restore objects without this flag with the gpu blitter and only objects
carrying the flag using TTM memcpy.
Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
defer for a later audit which vms actually need it. Most importantly, user-
allocated vms with pinned page-table objects can be restored using the
blitter.
Performance-wise memcpy restore is probably as fast as gpu restore if not
faster, but using gpu restore will help tackling future restrictions in
mappable LMEM size.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
17 files changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..8208fd5b72c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 118691ce81d7..fa2ba9e2a4d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -294,13 +294,16 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_USER BIT(3)
/* Object is allowed to lose its contents on suspend / resume, even if pinned */
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
+/* Object needs to be restored early using memcpy during resume */
+#define I915_BO_ALLOC_PM_EARLY BIT(5)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
- I915_BO_ALLOC_PM_VOLATILE)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+#define I915_BO_READONLY BIT(6)
+#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8736ae1dfbb2..c4a75e1c12ee 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
* More objects may have become unpinned as requests were
* retired. Now try to evict again. The gt may be wedged here
* in which case we automatically fall back to memcpy.
+ * We allow also backing up pinned objects that have not been
+ * marked for early recover, and that may contain, for example,
+ * page-tables for the migrate context.
*/
- ret = lmem_suspend(i915, true, false);
+ ret = lmem_suspend(i915, true, true);
if (ret)
goto out_recover;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index a87419755d43..2684daaa2f22 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
- if (!pm_apply->backup_pinned)
+ if (!pm_apply->backup_pinned ||
+ (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
@@ -156,7 +157,8 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
if (!backup)
return 0;
- if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ if (!pm_apply->allow_gpu && ((obj->flags & I915_BO_ALLOC_USER) ||
+ !(obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
err = i915_gem_object_lock(backup, apply->ww);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 0827634c842c..77d84a9e8789 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..890191f286e3 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
mutex_init(&ppgtt->flush);
mutex_init(&ppgtt->pin_mutex);
- ppgtt_init(&ppgtt->base, gt);
+ ppgtt_init(&ppgtt->base, gt, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6a5af995f5b1..037a9a6e4889 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
* space.
*
*/
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
int err;
@@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(ppgtt, gt);
+ ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index b9028c2ad3c7..f541d19264b4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -12,7 +12,9 @@ struct i915_address_space;
struct intel_gt;
enum i915_cache_level;
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
+
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8d71f67926f1..b99b26201b67 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
struct i915_ppgtt *ppgtt;
int err;
- ppgtt = i915_ppgtt_create(ggtt->vm.gt);
+ ppgtt = i915_ppgtt_create(ggtt->vm.gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2aeaae036a6f..c4e33b3a55b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
static struct i915_address_space *kernel_vm(struct intel_gt *gt)
{
if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
- return &i915_ppgtt_create(gt)->vm;
+ return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
else
return i915_vm_get(>->ggtt->vm);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index a0c2b952aa57..67d14afa6623 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
* used the passed in size for the page size, which should ensure it
* also has the same alignment.
*/
- obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
+ obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
+ vm->lmem_pt_obj_flags);
/*
* Ensure all paging structures for this vm share the same dma-resv
* object underneath, with the idea that one object_lock() will lock
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 5b539bd7645d..bc6750263359 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -260,6 +260,9 @@ struct i915_address_space {
u8 pd_shift;
u8 scratch_order;
+ /* Flags used when creating page-table objects for this vm */
+ unsigned long lmem_pt_obj_flags;
+
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
@@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
int i915_ggtt_probe_hw(struct drm_i915_private *i915);
int i915_ggtt_init_hw(struct drm_i915_private *i915);
@@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
int i915_ppgtt_init_hw(struct intel_gt *gt);
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
void i915_ggtt_suspend(struct i915_ggtt *gtt);
void i915_ggtt_resume(struct i915_ggtt *ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 1dac21aa7e5c..afb1cce9a352 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* TODO: Add support for huge LMEM PTEs
*/
- vm = i915_ppgtt_create(gt);
+ vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(vm))
return ERR_CAST(vm);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 886060f7e6fc..4396bfd630d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
}
static struct i915_ppgtt *
-__ppgtt_create(struct intel_gt *gt)
+__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
{
if (GRAPHICS_VER(gt->i915) < 8)
return gen6_ppgtt_create(gt);
else
- return gen8_ppgtt_create(gt);
+ return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
}
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
- ppgtt = __ppgtt_create(gt);
+ ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
if (IS_ERR(ppgtt))
return ppgtt;
@@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
return 0;
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct drm_i915_private *i915 = gt->i915;
@@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = i915->drm.dev;
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
dma_resv_init(&ppgtt->vm._resv);
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 7e6fdabac599..7e2d99dd012d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
return 0;
- ppgtt = i915_ppgtt_create(gt);
+ ppgtt = i915_ppgtt_create(gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b56a8e37a3cd..0d18e13e3468 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
enum intel_engine_id i;
int ret;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2d60a5a5b065..46f4236039a9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* [Intel-gfx] [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-14 19:31 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-14 19:31 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
We really only need memcpy restore for objects that affect the
operability of the migrate context. That is, primarily the page-table
objects of the migrate VM.
Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
restores using memcpy and a way to assign LMEM page-table object flags
to be used by the vms.
Restore objects without this flag with the gpu blitter and only objects
carrying the flag using TTM memcpy.
Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
defer for a later audit which vms actually need it. Most importantly, user-
allocated vms with pinned page-table objects can be restored using the
blitter.
Performance-wise memcpy restore is probably as fast as gpu restore if not
faster, but using gpu restore will help tackling future restrictions in
mappable LMEM size.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
17 files changed, 48 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..8208fd5b72c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 118691ce81d7..fa2ba9e2a4d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -294,13 +294,16 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_USER BIT(3)
/* Object is allowed to lose its contents on suspend / resume, even if pinned */
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
+/* Object needs to be restored early using memcpy during resume */
+#define I915_BO_ALLOC_PM_EARLY BIT(5)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
- I915_BO_ALLOC_PM_VOLATILE)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+#define I915_BO_READONLY BIT(6)
+#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8736ae1dfbb2..c4a75e1c12ee 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
* More objects may have become unpinned as requests were
* retired. Now try to evict again. The gt may be wedged here
* in which case we automatically fall back to memcpy.
+ * We allow also backing up pinned objects that have not been
+ * marked for early recover, and that may contain, for example,
+ * page-tables for the migrate context.
*/
- ret = lmem_suspend(i915, true, false);
+ ret = lmem_suspend(i915, true, true);
if (ret)
goto out_recover;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index a87419755d43..2684daaa2f22 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
- if (!pm_apply->backup_pinned)
+ if (!pm_apply->backup_pinned ||
+ (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
@@ -156,7 +157,8 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
if (!backup)
return 0;
- if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ if (!pm_apply->allow_gpu && ((obj->flags & I915_BO_ALLOC_USER) ||
+ !(obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
err = i915_gem_object_lock(backup, apply->ww);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 0827634c842c..77d84a9e8789 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..890191f286e3 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
mutex_init(&ppgtt->flush);
mutex_init(&ppgtt->pin_mutex);
- ppgtt_init(&ppgtt->base, gt);
+ ppgtt_init(&ppgtt->base, gt, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6a5af995f5b1..037a9a6e4889 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
* space.
*
*/
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
int err;
@@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(ppgtt, gt);
+ ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index b9028c2ad3c7..f541d19264b4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -12,7 +12,9 @@ struct i915_address_space;
struct intel_gt;
enum i915_cache_level;
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
+
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8d71f67926f1..b99b26201b67 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
struct i915_ppgtt *ppgtt;
int err;
- ppgtt = i915_ppgtt_create(ggtt->vm.gt);
+ ppgtt = i915_ppgtt_create(ggtt->vm.gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2aeaae036a6f..c4e33b3a55b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
static struct i915_address_space *kernel_vm(struct intel_gt *gt)
{
if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
- return &i915_ppgtt_create(gt)->vm;
+ return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
else
return i915_vm_get(>->ggtt->vm);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index a0c2b952aa57..67d14afa6623 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
* used the passed in size for the page size, which should ensure it
* also has the same alignment.
*/
- obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
+ obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
+ vm->lmem_pt_obj_flags);
/*
* Ensure all paging structures for this vm share the same dma-resv
* object underneath, with the idea that one object_lock() will lock
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 5b539bd7645d..bc6750263359 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -260,6 +260,9 @@ struct i915_address_space {
u8 pd_shift;
u8 scratch_order;
+ /* Flags used when creating page-table objects for this vm */
+ unsigned long lmem_pt_obj_flags;
+
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
@@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
int i915_ggtt_probe_hw(struct drm_i915_private *i915);
int i915_ggtt_init_hw(struct drm_i915_private *i915);
@@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
int i915_ppgtt_init_hw(struct intel_gt *gt);
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
void i915_ggtt_suspend(struct i915_ggtt *gtt);
void i915_ggtt_resume(struct i915_ggtt *ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 1dac21aa7e5c..afb1cce9a352 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* TODO: Add support for huge LMEM PTEs
*/
- vm = i915_ppgtt_create(gt);
+ vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(vm))
return ERR_CAST(vm);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 886060f7e6fc..4396bfd630d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
}
static struct i915_ppgtt *
-__ppgtt_create(struct intel_gt *gt)
+__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
{
if (GRAPHICS_VER(gt->i915) < 8)
return gen6_ppgtt_create(gt);
else
- return gen8_ppgtt_create(gt);
+ return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
}
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
- ppgtt = __ppgtt_create(gt);
+ ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
if (IS_ERR(ppgtt))
return ppgtt;
@@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
return 0;
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct drm_i915_private *i915 = gt->i915;
@@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = i915->drm.dev;
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
dma_resv_init(&ppgtt->vm._resv);
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 7e6fdabac599..7e2d99dd012d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
return 0;
- ppgtt = i915_ppgtt_create(gt);
+ ppgtt = i915_ppgtt_create(gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b56a8e37a3cd..0d18e13e3468 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
enum intel_engine_id i;
int ret;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2d60a5a5b065..46f4236039a9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
--
2.31.1
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-20 11:05 ` Matthew Auld
-1 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 11:05 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> We really only need memcpy restore for objects that affect the
> operability of the migrate context. That is, primarily the page-table
> objects of the migrate VM.
>
> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
> restores using memcpy and a way to assign LMEM page-table object flags
> to be used by the vms.
>
> Restore objects without this flag with the gpu blitter and only objects
> carrying the flag using TTM memcpy.
>
> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
> defer for a later audit which vms actually need it. Most importantly, user-
> allocated vms with pinned page-table objects can be restored using the
> blitter.
>
> Performance-wise memcpy restore is probably as fast as gpu restore if not
> faster, but using gpu restore will help tackling future restrictions in
> mappable LMEM size.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> 17 files changed, 48 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c2ab0e22db0a..8208fd5b72c3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
> } else if (HAS_FULL_PPGTT(i915)) {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt)) {
> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
> PTR_ERR(ppgtt));
> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
> if (args->flags)
> return -EINVAL;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 118691ce81d7..fa2ba9e2a4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> #define I915_BO_ALLOC_USER BIT(3)
> /* Object is allowed to lose its contents on suspend / resume, even if pinned */
> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> +/* Object needs to be restored early using memcpy during resume */
> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> I915_BO_ALLOC_VOLATILE | \
> I915_BO_ALLOC_CPU_CLEAR | \
> I915_BO_ALLOC_USER | \
> - I915_BO_ALLOC_PM_VOLATILE)
> -#define I915_BO_READONLY BIT(5)
> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
> + I915_BO_ALLOC_PM_VOLATILE | \
> + I915_BO_ALLOC_PM_EARLY)
> +#define I915_BO_READONLY BIT(6)
> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
>
> /**
> * @mem_flags - Mutable placement-related flags
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 8736ae1dfbb2..c4a75e1c12ee 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
> * More objects may have become unpinned as requests were
> * retired. Now try to evict again. The gt may be wedged here
> * in which case we automatically fall back to memcpy.
> + * We allow also backing up pinned objects that have not been
> + * marked for early recover, and that may contain, for example,
> + * page-tables for the migrate context.
> */
> - ret = lmem_suspend(i915, true, false);
> + ret = lmem_suspend(i915, true, true);
I guess we could have made these flags instead of bools, for better
readability. I've already forgotten which is which :)
> if (ret)
> goto out_recover;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> index a87419755d43..2684daaa2f22 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>
> - if (!pm_apply->backup_pinned)
> + if (!pm_apply->backup_pinned ||
> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> @@ -156,7 +157,8 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> if (!backup)
> return 0;
>
> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + if (!pm_apply->allow_gpu && ((obj->flags & I915_BO_ALLOC_USER) ||
> + !(obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> err = i915_gem_object_lock(backup, apply->ww);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 0827634c842c..77d84a9e8789 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_unlock;
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 1aee5e6b1b23..890191f286e3 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
> mutex_init(&ppgtt->flush);
> mutex_init(&ppgtt->pin_mutex);
>
> - ppgtt_init(&ppgtt->base, gt);
> + ppgtt_init(&ppgtt->base, gt, 0);
> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
> ppgtt->base.vm.top = 1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 6a5af995f5b1..037a9a6e4889 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> * space.
> *
> */
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
> int err;
> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - ppgtt_init(ppgtt, gt);
> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index b9028c2ad3c7..f541d19264b4 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -12,7 +12,9 @@ struct i915_address_space;
> struct intel_gt;
> enum i915_cache_level;
>
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
> +
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> u32 flags);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 8d71f67926f1..b99b26201b67 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> struct i915_ppgtt *ppgtt;
> int err;
>
> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, I915_BO_ALLOC_PM_EARLY);
I guess could leave as flags=0, since appgtt is not relevant on
discrete/modern hw(?).
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2aeaae036a6f..c4e33b3a55b4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
> static struct i915_address_space *kernel_vm(struct intel_gt *gt)
> {
> if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
> - return &i915_ppgtt_create(gt)->vm;
> + return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
> else
> return i915_vm_get(>->ggtt->vm);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index a0c2b952aa57..67d14afa6623 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
> * used the passed in size for the page size, which should ensure it
> * also has the same alignment.
> */
> - obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
> + vm->lmem_pt_obj_flags);
> /*
> * Ensure all paging structures for this vm share the same dma-resv
> * object underneath, with the idea that one object_lock() will lock
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 5b539bd7645d..bc6750263359 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -260,6 +260,9 @@ struct i915_address_space {
> u8 pd_shift;
> u8 scratch_order;
>
> + /* Flags used when creating page-table objects for this vm */
> + unsigned long lmem_pt_obj_flags;
> +
> struct drm_i915_gem_object *
> (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
>
> @@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
> int i915_ggtt_init_hw(struct drm_i915_private *i915);
> @@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
>
> int i915_ppgtt_init_hw(struct intel_gt *gt);
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> void i915_ggtt_suspend(struct i915_ggtt *gtt);
> void i915_ggtt_resume(struct i915_ggtt *ggtt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 1dac21aa7e5c..afb1cce9a352 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> * TODO: Add support for huge LMEM PTEs
> */
>
> - vm = i915_ppgtt_create(gt);
> + vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(vm))
> return ERR_CAST(vm);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 886060f7e6fc..4396bfd630d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> }
>
> static struct i915_ppgtt *
> -__ppgtt_create(struct intel_gt *gt)
> +__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
> {
> if (GRAPHICS_VER(gt->i915) < 8)
> return gen6_ppgtt_create(gt);
> else
> - return gen8_ppgtt_create(gt);
> + return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
> }
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = __ppgtt_create(gt);
> + ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
> if (IS_ERR(ppgtt))
> return ppgtt;
>
> @@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
> return 0;
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct drm_i915_private *i915 = gt->i915;
>
> @@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = i915->drm.dev;
> ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> + ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
>
> dma_resv_init(&ppgtt->vm._resv);
> i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 7e6fdabac599..7e2d99dd012d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
> if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
> return 0;
>
> - ppgtt = i915_ppgtt_create(gt);
> + ppgtt = i915_ppgtt_create(gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index b56a8e37a3cd..0d18e13e3468 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
> enum intel_engine_id i;
> int ret;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 2d60a5a5b065..46f4236039a9 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (!HAS_PPGTT(dev_priv))
> return 0;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
> if (IS_ERR(file))
> return PTR_ERR(file);
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_free;
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Intel-gfx] [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-20 11:05 ` Matthew Auld
0 siblings, 0 replies; 37+ messages in thread
From: Matthew Auld @ 2021-09-20 11:05 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 14/09/2021 20:31, Thomas Hellström wrote:
> We really only need memcpy restore for objects that affect the
> operability of the migrate context. That is, primarily the page-table
> objects of the migrate VM.
>
> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
> restores using memcpy and a way to assign LMEM page-table object flags
> to be used by the vms.
>
> Restore objects without this flag with the gpu blitter and only objects
> carrying the flag using TTM memcpy.
>
> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
> defer for a later audit which vms actually need it. Most importantly, user-
> allocated vms with pinned page-table objects can be restored using the
> blitter.
>
> Performance-wise memcpy restore is probably as fast as gpu restore if not
> faster, but using gpu restore will help tackling future restrictions in
> mappable LMEM size.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> 17 files changed, 48 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c2ab0e22db0a..8208fd5b72c3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
> } else if (HAS_FULL_PPGTT(i915)) {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt)) {
> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
> PTR_ERR(ppgtt));
> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
> if (args->flags)
> return -EINVAL;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 118691ce81d7..fa2ba9e2a4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> #define I915_BO_ALLOC_USER BIT(3)
> /* Object is allowed to lose its contents on suspend / resume, even if pinned */
> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> +/* Object needs to be restored early using memcpy during resume */
> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> I915_BO_ALLOC_VOLATILE | \
> I915_BO_ALLOC_CPU_CLEAR | \
> I915_BO_ALLOC_USER | \
> - I915_BO_ALLOC_PM_VOLATILE)
> -#define I915_BO_READONLY BIT(5)
> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
> + I915_BO_ALLOC_PM_VOLATILE | \
> + I915_BO_ALLOC_PM_EARLY)
> +#define I915_BO_READONLY BIT(6)
> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
>
> /**
> * @mem_flags - Mutable placement-related flags
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 8736ae1dfbb2..c4a75e1c12ee 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
> * More objects may have become unpinned as requests were
> * retired. Now try to evict again. The gt may be wedged here
> * in which case we automatically fall back to memcpy.
> + * We allow also backing up pinned objects that have not been
> + * marked for early recover, and that may contain, for example,
> + * page-tables for the migrate context.
> */
> - ret = lmem_suspend(i915, true, false);
> + ret = lmem_suspend(i915, true, true);
I guess we could have made these flags instead of bools, for better
readability. I've already forgotten which is which :)
> if (ret)
> goto out_recover;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> index a87419755d43..2684daaa2f22 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>
> - if (!pm_apply->backup_pinned)
> + if (!pm_apply->backup_pinned ||
> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> @@ -156,7 +157,8 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> if (!backup)
> return 0;
>
> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + if (!pm_apply->allow_gpu && ((obj->flags & I915_BO_ALLOC_USER) ||
> + !(obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> err = i915_gem_object_lock(backup, apply->ww);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 0827634c842c..77d84a9e8789 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_unlock;
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 1aee5e6b1b23..890191f286e3 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
> mutex_init(&ppgtt->flush);
> mutex_init(&ppgtt->pin_mutex);
>
> - ppgtt_init(&ppgtt->base, gt);
> + ppgtt_init(&ppgtt->base, gt, 0);
> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
> ppgtt->base.vm.top = 1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 6a5af995f5b1..037a9a6e4889 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> * space.
> *
> */
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
> int err;
> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - ppgtt_init(ppgtt, gt);
> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index b9028c2ad3c7..f541d19264b4 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -12,7 +12,9 @@ struct i915_address_space;
> struct intel_gt;
> enum i915_cache_level;
>
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
> +
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> u32 flags);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 8d71f67926f1..b99b26201b67 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> struct i915_ppgtt *ppgtt;
> int err;
>
> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, I915_BO_ALLOC_PM_EARLY);
I guess could leave as flags=0, since appgtt is not relevant on
discrete/modern hw(?).
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2aeaae036a6f..c4e33b3a55b4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
> static struct i915_address_space *kernel_vm(struct intel_gt *gt)
> {
> if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
> - return &i915_ppgtt_create(gt)->vm;
> + return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
> else
> return i915_vm_get(>->ggtt->vm);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index a0c2b952aa57..67d14afa6623 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
> * used the passed in size for the page size, which should ensure it
> * also has the same alignment.
> */
> - obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
> + vm->lmem_pt_obj_flags);
> /*
> * Ensure all paging structures for this vm share the same dma-resv
> * object underneath, with the idea that one object_lock() will lock
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 5b539bd7645d..bc6750263359 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -260,6 +260,9 @@ struct i915_address_space {
> u8 pd_shift;
> u8 scratch_order;
>
> + /* Flags used when creating page-table objects for this vm */
> + unsigned long lmem_pt_obj_flags;
> +
> struct drm_i915_gem_object *
> (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
>
> @@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
> int i915_ggtt_init_hw(struct drm_i915_private *i915);
> @@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
>
> int i915_ppgtt_init_hw(struct intel_gt *gt);
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> void i915_ggtt_suspend(struct i915_ggtt *gtt);
> void i915_ggtt_resume(struct i915_ggtt *ggtt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 1dac21aa7e5c..afb1cce9a352 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> * TODO: Add support for huge LMEM PTEs
> */
>
> - vm = i915_ppgtt_create(gt);
> + vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(vm))
> return ERR_CAST(vm);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 886060f7e6fc..4396bfd630d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> }
>
> static struct i915_ppgtt *
> -__ppgtt_create(struct intel_gt *gt)
> +__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
> {
> if (GRAPHICS_VER(gt->i915) < 8)
> return gen6_ppgtt_create(gt);
> else
> - return gen8_ppgtt_create(gt);
> + return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
> }
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = __ppgtt_create(gt);
> + ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
> if (IS_ERR(ppgtt))
> return ppgtt;
>
> @@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
> return 0;
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct drm_i915_private *i915 = gt->i915;
>
> @@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = i915->drm.dev;
> ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> + ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
>
> dma_resv_init(&ppgtt->vm._resv);
> i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 7e6fdabac599..7e2d99dd012d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
> if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
> return 0;
>
> - ppgtt = i915_ppgtt_create(gt);
> + ppgtt = i915_ppgtt_create(gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index b56a8e37a3cd..0d18e13e3468 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
> enum intel_engine_id i;
> int ret;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 2d60a5a5b065..46f4236039a9 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (!HAS_PPGTT(dev_priv))
> return 0;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
> if (IS_ERR(file))
> return PTR_ERR(file);
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_free;
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-20 11:05 ` [Intel-gfx] " Matthew Auld
@ 2021-09-20 11:09 ` Thomas Hellström
-1 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-20 11:09 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On Mon, 2021-09-20 at 12:05 +0100, Matthew Auld wrote:
> On 14/09/2021 20:31, Thomas Hellström wrote:
> > We really only need memcpy restore for objects that affect the
> > operability of the migrate context. That is, primarily the page-
> > table
> > objects of the migrate VM.
> >
> > Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need
> > early
> > restores using memcpy and a way to assign LMEM page-table object
> > flags
> > to be used by the vms.
> >
> > Restore objects without this flag with the gpu blitter and only
> > objects
> > carrying the flag using TTM memcpy.
> >
> > Initially mark the migrate, gt, gtt and vgpu vms to use this flag,
> > and
> > defer for a later audit which vms actually need it. Most
> > importantly, user-
> > allocated vms with pinned page-table objects can be restored using
> > the
> > blitter.
> >
> > Performance-wise memcpy restore is probably as fast as gpu restore
> > if not
> > faster, but using gpu restore will help tackling future
> > restrictions in
> > mappable LMEM size.
> >
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> > drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
> > drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
> > drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> > drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> > drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> > drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++---
> > --
> > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> > drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> > 17 files changed, 48 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index c2ab0e22db0a..8208fd5b72c3 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct
> > drm_i915_private *i915,
> > } else if (HAS_FULL_PPGTT(i915)) {
> > struct i915_ppgtt *ppgtt;
> >
> > - ppgtt = i915_ppgtt_create(&i915->gt);
> > + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> > if (IS_ERR(ppgtt)) {
> > drm_dbg(&i915->drm, "PPGTT setup failed
> > (%ld)\n",
> > PTR_ERR(ppgtt));
> > @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct
> > drm_device *dev, void *data,
> > if (args->flags)
> > return -EINVAL;
> >
> > - ppgtt = i915_ppgtt_create(&i915->gt);
> > + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> > if (IS_ERR(ppgtt))
> > return PTR_ERR(ppgtt);
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index 118691ce81d7..fa2ba9e2a4d0 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> > #define I915_BO_ALLOC_USER BIT(3)
> > /* Object is allowed to lose its contents on suspend / resume,
> > even if pinned */
> > #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> > +/* Object needs to be restored early using memcpy during resume */
> > +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> > #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> > I915_BO_ALLOC_VOLATILE | \
> > I915_BO_ALLOC_CPU_CLEAR | \
> > I915_BO_ALLOC_USER | \
> > - I915_BO_ALLOC_PM_VOLATILE)
> > -#define I915_BO_READONLY BIT(5)
> > -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not
> > release! */
> > + I915_BO_ALLOC_PM_VOLATILE | \
> > + I915_BO_ALLOC_PM_EARLY)
> > +#define I915_BO_READONLY BIT(6)
> > +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not
> > release! */
> >
> > /**
> > * @mem_flags - Mutable placement-related flags
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > index 8736ae1dfbb2..c4a75e1c12ee 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > @@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct
> > drm_i915_private *i915)
> > * More objects may have become unpinned as requests were
> > * retired. Now try to evict again. The gt may be wedged
> > here
> > * in which case we automatically fall back to memcpy.
> > + * We allow also backing up pinned objects that have not
> > been
> > + * marked for early recover, and that may contain, for
> > example,
> > + * page-tables for the migrate context.
> > */
> > - ret = lmem_suspend(i915, true, false);
> > + ret = lmem_suspend(i915, true, true);
>
> I guess we could have made these flags instead of bools, for better
> readability. I've already forgotten which is which :)
>
> > if (ret)
> > goto out_recover;
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > index a87419755d43..2684daaa2f22 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct
> > i915_gem_apply_to_region *apply,
> > if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> > return ttm_bo_validate(bo,
> > i915_ttm_sys_placement(), &ctx);
> >
> > - if (!pm_apply->backup_pinned)
> > + if (!pm_apply->backup_pinned ||
> > + (pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_PM_EARLY)))
> > return 0;
> >
> > if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> > @@ -156,7 +157,8 @@ static int i915_ttm_restore(struct
> > i915_gem_apply_to_region *apply,
> > if (!backup)
> > return 0;
> >
> > - if (!pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_USER))
> > + if (!pm_apply->allow_gpu && ((obj->flags &
> > I915_BO_ALLOC_USER) ||
> > + !(obj->flags &
> > I915_BO_ALLOC_PM_EARLY)))
> > return 0;
> >
> > err = i915_gem_object_lock(backup, apply->ww);
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > index 0827634c842c..77d84a9e8789 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> > mkwrite_device_info(dev_priv)->ppgtt_type =
> > INTEL_PPGTT_FULL;
> > mkwrite_device_info(dev_priv)->ppgtt_size = 48;
> >
> > - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> > + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> > if (IS_ERR(ppgtt)) {
> > err = PTR_ERR(ppgtt);
> > goto out_unlock;
> > diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > index 1aee5e6b1b23..890191f286e3 100644
> > --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct
> > intel_gt *gt)
> > mutex_init(&ppgtt->flush);
> > mutex_init(&ppgtt->pin_mutex);
> >
> > - ppgtt_init(&ppgtt->base, gt);
> > + ppgtt_init(&ppgtt->base, gt, 0);
> > ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K /
> > sizeof(gen6_pte_t));
> > ppgtt->base.vm.top = 1;
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > index 6a5af995f5b1..037a9a6e4889 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space
> > *vm)
> > * space.
> > *
> > */
> > -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> > +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> > + unsigned long
> > lmem_pt_obj_flags)
> > {
> > struct i915_ppgtt *ppgtt;
> > int err;
> > @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
> > intel_gt *gt)
> > if (!ppgtt)
> > return ERR_PTR(-ENOMEM);
> >
> > - ppgtt_init(ppgtt, gt);
> > + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> > ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> > ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K /
> > sizeof(gen8_pte_t));
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > index b9028c2ad3c7..f541d19264b4 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > @@ -12,7 +12,9 @@ struct i915_address_space;
> > struct intel_gt;
> > enum i915_cache_level;
> >
> > -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> > +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> > + unsigned long
> > lmem_pt_obj_flags);
> > +
> > u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > enum i915_cache_level level,
> > u32 flags);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index 8d71f67926f1..b99b26201b67 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
> > *ggtt)
> > struct i915_ppgtt *ppgtt;
> > int err;
> >
> > - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> > + ppgtt = i915_ppgtt_create(ggtt->vm.gt,
> > I915_BO_ALLOC_PM_EARLY);
>
> I guess could leave as flags=0, since appgtt is not relevant on
> discrete/modern hw(?).
>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
True, I'll fix these up.
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [Intel-gfx] [PATCH v3 6/6] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-20 11:09 ` Thomas Hellström
0 siblings, 0 replies; 37+ messages in thread
From: Thomas Hellström @ 2021-09-20 11:09 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On Mon, 2021-09-20 at 12:05 +0100, Matthew Auld wrote:
> On 14/09/2021 20:31, Thomas Hellström wrote:
> > We really only need memcpy restore for objects that affect the
> > operability of the migrate context. That is, primarily the page-
> > table
> > objects of the migrate VM.
> >
> > Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need
> > early
> > restores using memcpy and a way to assign LMEM page-table object
> > flags
> > to be used by the vms.
> >
> > Restore objects without this flag with the gpu blitter and only
> > objects
> > carrying the flag using TTM memcpy.
> >
> > Initially mark the migrate, gt, gtt and vgpu vms to use this flag,
> > and
> > defer for a later audit which vms actually need it. Most
> > importantly, user-
> > allocated vms with pinned page-table objects can be restored using
> > the
> > blitter.
> >
> > Performance-wise memcpy restore is probably as fast as gpu restore
> > if not
> > faster, but using gpu restore will help tackling future
> > restrictions in
> > mappable LMEM size.
> >
> > Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> > drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 5 ++++-
> > drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 6 ++++--
> > drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> > drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> > drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> > drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++---
> > --
> > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> > drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> > 17 files changed, 48 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index c2ab0e22db0a..8208fd5b72c3 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct
> > drm_i915_private *i915,
> > } else if (HAS_FULL_PPGTT(i915)) {
> > struct i915_ppgtt *ppgtt;
> >
> > - ppgtt = i915_ppgtt_create(&i915->gt);
> > + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> > if (IS_ERR(ppgtt)) {
> > drm_dbg(&i915->drm, "PPGTT setup failed
> > (%ld)\n",
> > PTR_ERR(ppgtt));
> > @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct
> > drm_device *dev, void *data,
> > if (args->flags)
> > return -EINVAL;
> >
> > - ppgtt = i915_ppgtt_create(&i915->gt);
> > + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> > if (IS_ERR(ppgtt))
> > return PTR_ERR(ppgtt);
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > index 118691ce81d7..fa2ba9e2a4d0 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> > @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> > #define I915_BO_ALLOC_USER BIT(3)
> > /* Object is allowed to lose its contents on suspend / resume,
> > even if pinned */
> > #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> > +/* Object needs to be restored early using memcpy during resume */
> > +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> > #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> > I915_BO_ALLOC_VOLATILE | \
> > I915_BO_ALLOC_CPU_CLEAR | \
> > I915_BO_ALLOC_USER | \
> > - I915_BO_ALLOC_PM_VOLATILE)
> > -#define I915_BO_READONLY BIT(5)
> > -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not
> > release! */
> > + I915_BO_ALLOC_PM_VOLATILE | \
> > + I915_BO_ALLOC_PM_EARLY)
> > +#define I915_BO_READONLY BIT(6)
> > +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not
> > release! */
> >
> > /**
> > * @mem_flags - Mutable placement-related flags
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > index 8736ae1dfbb2..c4a75e1c12ee 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> > @@ -98,8 +98,11 @@ int i915_gem_backup_suspend(struct
> > drm_i915_private *i915)
> > * More objects may have become unpinned as requests were
> > * retired. Now try to evict again. The gt may be wedged
> > here
> > * in which case we automatically fall back to memcpy.
> > + * We allow also backing up pinned objects that have not
> > been
> > + * marked for early recover, and that may contain, for
> > example,
> > + * page-tables for the migrate context.
> > */
> > - ret = lmem_suspend(i915, true, false);
> > + ret = lmem_suspend(i915, true, true);
>
> I guess we could have made these flags instead of bools, for better
> readability. I've already forgotten which is which :)
>
> > if (ret)
> > goto out_recover;
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > index a87419755d43..2684daaa2f22 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> > @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct
> > i915_gem_apply_to_region *apply,
> > if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> > return ttm_bo_validate(bo,
> > i915_ttm_sys_placement(), &ctx);
> >
> > - if (!pm_apply->backup_pinned)
> > + if (!pm_apply->backup_pinned ||
> > + (pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_PM_EARLY)))
> > return 0;
> >
> > if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> > @@ -156,7 +157,8 @@ static int i915_ttm_restore(struct
> > i915_gem_apply_to_region *apply,
> > if (!backup)
> > return 0;
> >
> > - if (!pm_apply->allow_gpu && (obj->flags &
> > I915_BO_ALLOC_USER))
> > + if (!pm_apply->allow_gpu && ((obj->flags &
> > I915_BO_ALLOC_USER) ||
> > + !(obj->flags &
> > I915_BO_ALLOC_PM_EARLY)))
> > return 0;
> >
> > err = i915_gem_object_lock(backup, apply->ww);
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > index 0827634c842c..77d84a9e8789 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> > @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> > mkwrite_device_info(dev_priv)->ppgtt_type =
> > INTEL_PPGTT_FULL;
> > mkwrite_device_info(dev_priv)->ppgtt_size = 48;
> >
> > - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> > + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> > if (IS_ERR(ppgtt)) {
> > err = PTR_ERR(ppgtt);
> > goto out_unlock;
> > diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > index 1aee5e6b1b23..890191f286e3 100644
> > --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> > @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct
> > intel_gt *gt)
> > mutex_init(&ppgtt->flush);
> > mutex_init(&ppgtt->pin_mutex);
> >
> > - ppgtt_init(&ppgtt->base, gt);
> > + ppgtt_init(&ppgtt->base, gt, 0);
> > ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K /
> > sizeof(gen6_pte_t));
> > ppgtt->base.vm.top = 1;
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > index 6a5af995f5b1..037a9a6e4889 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space
> > *vm)
> > * space.
> > *
> > */
> > -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> > +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> > + unsigned long
> > lmem_pt_obj_flags)
> > {
> > struct i915_ppgtt *ppgtt;
> > int err;
> > @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
> > intel_gt *gt)
> > if (!ppgtt)
> > return ERR_PTR(-ENOMEM);
> >
> > - ppgtt_init(ppgtt, gt);
> > + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> > ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> > ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K /
> > sizeof(gen8_pte_t));
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > index b9028c2ad3c7..f541d19264b4 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > @@ -12,7 +12,9 @@ struct i915_address_space;
> > struct intel_gt;
> > enum i915_cache_level;
> >
> > -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> > +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> > + unsigned long
> > lmem_pt_obj_flags);
> > +
> > u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > enum i915_cache_level level,
> > u32 flags);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index 8d71f67926f1..b99b26201b67 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
> > *ggtt)
> > struct i915_ppgtt *ppgtt;
> > int err;
> >
> > - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> > + ppgtt = i915_ppgtt_create(ggtt->vm.gt,
> > I915_BO_ALLOC_PM_EARLY);
>
> I guess could leave as flags=0, since appgtt is not relevant on
> discrete/modern hw(?).
>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
True, I'll fix these up.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
` (6 preceding siblings ...)
(?)
@ 2021-09-14 19:40 ` Patchwork
-1 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2021-09-14 19:40 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c4b15f1489b7 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
329f8dcaaa17 drm/i915/gem: Implement a function to process all gem objects of a region
05ab254d5b1f drm/i915 Implement LMEM backup and restore for suspend / resume
-:294: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#294:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 490 lines checked
d7decd7ad236 drm/i915/gt: Register the migrate contexts with their engines
21ff3e091982 drm/i915: Don't back up pinned LMEM context images and rings during suspend
62cf1113c535 drm/i915: Reduce the number of objects subject to memcpy recover
^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
` (7 preceding siblings ...)
(?)
@ 2021-09-14 20:06 ` Patchwork
-1 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2021-09-14 20:06 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2006 bytes --]
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10584 -> Patchwork_21046
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/index.html
Known issues
------------
Here are the changes found in Patchwork_21046 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
Participating hosts (39 -> 38)
------------------------------
Additional (3): fi-kbl-soraka fi-tgl-1115g4 fi-kbl-guc
Missing (4): fi-bdw-samus fi-bsw-cyan bat-dg1-6 bat-dg1-5
Build changes
-------------
* Linux: CI_DRM_10584 -> Patchwork_21046
CI-20190529: 20190529
CI_DRM_10584: 7fa18a9066276df7e4c9ffe45c98f4604bd92bdd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6209: 07d6594ed02f55b68d64fa6dd7f80cfbc1ce4ef8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21046: 62cf1113c535090369956f6de8583f56418ba8d1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
62cf1113c535 drm/i915: Reduce the number of objects subject to memcpy recover
21ff3e091982 drm/i915: Don't back up pinned LMEM context images and rings during suspend
d7decd7ad236 drm/i915/gt: Register the migrate contexts with their engines
05ab254d5b1f drm/i915 Implement LMEM backup and restore for suspend / resume
329f8dcaaa17 drm/i915/gem: Implement a function to process all gem objects of a region
c4b15f1489b7 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/index.html
[-- Attachment #2: Type: text/html, Size: 2550 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
` (8 preceding siblings ...)
(?)
@ 2021-09-14 21:14 ` Patchwork
-1 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2021-09-14 21:14 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27391 bytes --]
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev4)
URL : https://patchwork.freedesktop.org/series/94278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10584_full -> Patchwork_21046_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21046_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21046_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21046_full:
### IGT changes ###
#### Possible regressions ####
* igt@dmabuf@all@dma_fence_chain:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl3/igt@dmabuf@all@dma_fence_chain.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl4/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_schedule@submit-golden-slice@rcs0:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb7/igt@gem_exec_schedule@submit-golden-slice@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@gem_exec_schedule@submit-golden-slice@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_21046_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +6 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][14] -> [SKIP][15] ([i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb2/igt@gem_huc_copy@huc-copy.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@gem_userptr_blits@unsync-unmap-after-close.html
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#3297])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-context:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#456])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb1/igt@gem_workarounds@suspend-resume-context.html
- shard-kbl: NOTRUN -> [INCOMPLETE][21] ([i915#155])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@gem_workarounds@suspend-resume-context.html
* igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#109289])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@gen7_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl10/igt@gen9_exec_parse@allowed-single.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-secure:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2856])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-param:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#2856])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_suspend@forcewake:
- shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([i915#2411] / [i915#456])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb6/igt@i915_suspend@forcewake.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb7/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#111614])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#110725] / [fdo#111614])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109278] / [i915#3886]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl3/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271]) +19 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl2/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +8 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl2/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl3/igt@kms_chamelium@vga-hpd-after-suspend.html
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +4 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_color@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109278] / [i915#1149])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@kms_color@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][43] ([i915#1319])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl2/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109279] / [i915#3359]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x170-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#3359]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278] / [fdo#109279]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-onscreen:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278]) +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-32x32-onscreen.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274] / [fdo#109278])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2122])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#3701])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271]) +85 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#111825]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109280]) +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#658])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][61] -> [SKIP][62] ([fdo#109441]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_writeback@writeback-check-output:
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#2437])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb6/igt@kms_writeback@writeback-check-output.html
* igt@perf@polling:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#1542]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl2/igt@perf@polling.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl7/igt@perf@polling.html
* igt@prime_nv_api@nv_self_import:
- shard-tglb: NOTRUN -> [SKIP][66] ([fdo#109291])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@prime_nv_api@nv_self_import.html
* igt@sysfs_clients@fair-1:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#2994])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@sysfs_clients@fair-1.html
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#2994])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb6/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@split-10:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-kbl: [INCOMPLETE][70] ([i915#4130]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl1/igt@core_hotunplug@unbind-rebind.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl6/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: [FAIL][72] ([i915#2842]) -> [PASS][73] +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-tglb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][74] ([i915#180]) -> [PASS][75] +4 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: [INCOMPLETE][76] ([i915#146] / [i915#198]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][78] ([i915#2122]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][80] ([i915#1188]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl1/igt@kms_hdr@bpc-switch.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][82] ([fdo#109441]) -> [PASS][83] +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
#### Warnings ####
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][84] ([i915#3288]) -> [FAIL][85] ([i915#3343])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][86] ([i915#1804] / [i915#2684]) -> [WARN][87] ([i915#2684])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-iclb: [SKIP][88] ([i915#658]) -> [SKIP][89] ([i915#2920]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][90] ([i915#2920]) -> [SKIP][91] ([i915#658]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl1/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl7/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl4/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl6/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl1/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl4/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl1/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-kbl4/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl7/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl7/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl6/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl4/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl3/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-kbl2/igt@runner@aborted.html
- shard-skl: ([FAIL][111], [FAIL][112]) ([i915#3002] / [i915#3363]) -> ([FAIL][113], [FAIL][114]) ([i915#1436] / [i915#3002] / [i915#3363])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl10/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10584/shard-skl2/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/shard-skl8/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3288]: https://gitlab.freedesktop.org/drm/intel/issues/3288
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3343]: https://gitlab.freedesktop.org/drm/intel/issues/3343
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
Participating hosts (11 -> 10)
------------------------------
Missing (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_10584 -> Patchwork_21046
CI-20190529: 20190529
CI_DRM_10584: 7fa18a9066276df7e4c9ffe45c98f4604bd92bdd @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6209: 07d6594ed02f55b68d64fa6dd7f80cfbc1ce4ef8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21046: 62cf1113c535090369956f6de8583f56418ba8d1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21046/index.html
[-- Attachment #2: Type: text/html, Size: 33827 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev5)
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
` (9 preceding siblings ...)
(?)
@ 2021-09-15 12:22 ` Patchwork
-1 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2021-09-15 12:22 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev5)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0dcc28cd9f83 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
0d5d3f0fbde1 drm/i915/gem: Implement a function to process all gem objects of a region
4fb1ade84390 drm/i915 Implement LMEM backup and restore for suspend / resume
-:294: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#294:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 490 lines checked
580679d858b8 drm/i915/gt: Register the migrate contexts with their engines
9376b1663615 drm/i915: Don't back up pinned LMEM context images and rings during suspend
cb6823a52864 drm/i915: Reduce the number of objects subject to memcpy recover
^ permalink raw reply [flat|nested] 37+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev5)
2021-09-14 19:31 ` [Intel-gfx] " Thomas Hellström
` (10 preceding siblings ...)
(?)
@ 2021-09-15 13:09 ` Patchwork
-1 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2021-09-15 13:09 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13697 bytes --]
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev5)
URL : https://patchwork.freedesktop.org/series/94278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10589 -> Patchwork_21056
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21056 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21056, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21056:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload:
- fi-kbl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-kbl-guc/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-kbl-guc/igt@i915_module_load@reload.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [INCOMPLETE][3] ([i915#4136]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-tgl-dsi/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-dsi/igt@i915_module_load@reload.html
Known issues
------------
Here are the changes found in Patchwork_21056 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6] ([i915#4130])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][7] ([i915#4130])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8700k: [PASS][8] -> [INCOMPLETE][9] ([i915#4130])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: NOTRUN -> [INCOMPLETE][10] ([i915#4130])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][11] ([i915#4130])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#2190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8109u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#3282])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@reload:
- fi-icl-y: [PASS][17] -> [TIMEOUT][18] ([i915#4136])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-icl-y/igt@i915_module_load@reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-y/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][19] ([i915#1155])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
- fi-rkl-11600: NOTRUN -> [SKIP][20] ([i915#3012])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@mman:
- fi-cfl-guc: NOTRUN -> [INCOMPLETE][21] ([i915#4129])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-guc/igt@i915_selftest@live@mman.html
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][22] ([i915#4129])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@i915_selftest@live@mman.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][23] ([fdo#111827]) +8 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][24] ([fdo#111827]) +8 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-cfl-8109u: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-icl-u2: NOTRUN -> [SKIP][26] ([fdo#109309]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600: NOTRUN -> [SKIP][27] ([i915#4103]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][28] ([i915#4103]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][29] ([fdo#109278]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][30] ([fdo#109285])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-11600: NOTRUN -> [SKIP][31] ([fdo#109285] / [i915#4098])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][32] ([fdo#109285])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-11600: NOTRUN -> [SKIP][33] ([i915#533])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8109u: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#533])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-cfl-8109u: NOTRUN -> [SKIP][35] ([fdo#109271]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@kms_psr@primary_mmap_gtt.html
- fi-rkl-11600: NOTRUN -> [SKIP][36] ([i915#1072]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][37] ([i915#1072]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][38] ([i915#3301])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][39] ([i915#3301])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-icl-u2/igt@prime_vgem@basic-userptr.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][40] ([i915#3301])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- fi-rkl-11600: NOTRUN -> [SKIP][41] ([i915#3291]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@prime_vgem@basic-write.html
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][42] ([i915#3928])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-rkl-11600/igt@runner@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][43] ([i915#1602] / [i915#2722])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u: [INCOMPLETE][44] ([i915#155]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-8109u/igt@gem_exec_suspend@basic-s0.html
* igt@i915_module_load@reload:
- fi-cfl-guc: [INCOMPLETE][46] -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-cfl-guc/igt@i915_module_load@reload.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-cfl-guc/igt@i915_module_load@reload.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][48] ([i915#2868]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10589/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4129]: https://gitlab.freedesktop.org/drm/intel/issues/4129
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (37 -> 35)
------------------------------
Additional (3): fi-rkl-11600 fi-icl-u2 fi-tgl-1115g4
Missing (5): fi-kbl-soraka bat-dg1-6 fi-skl-guc fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10589 -> Patchwork_21056
CI-20190529: 20190529
CI_DRM_10589: 18f191fdebda9b01b1dc0c41566605ce32a9b239 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6209: 07d6594ed02f55b68d64fa6dd7f80cfbc1ce4ef8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21056: cb6823a528641b9b5de752582a5426e6f3aa90f9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cb6823a52864 drm/i915: Reduce the number of objects subject to memcpy recover
9376b1663615 drm/i915: Don't back up pinned LMEM context images and rings during suspend
580679d858b8 drm/i915/gt: Register the migrate contexts with their engines
4fb1ade84390 drm/i915 Implement LMEM backup and restore for suspend / resume
0d5d3f0fbde1 drm/i915/gem: Implement a function to process all gem objects of a region
0dcc28cd9f83 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21056/index.html
[-- Attachment #2: Type: text/html, Size: 16641 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread