From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-22.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D797DC433F5 for ; Tue, 14 Sep 2021 20:48:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDB2B60F6F for ; Tue, 14 Sep 2021 20:48:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234621AbhINUtd (ORCPT ); Tue, 14 Sep 2021 16:49:33 -0400 Received: from mail-ot1-f49.google.com ([209.85.210.49]:34640 "EHLO mail-ot1-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234309AbhINUtZ (ORCPT ); Tue, 14 Sep 2021 16:49:25 -0400 Received: by mail-ot1-f49.google.com with SMTP id k12-20020a056830150c00b0051abe7f680bso444648otp.1 for ; Tue, 14 Sep 2021 13:48:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hfnaBiDsLPqKzOMV5CVhITztcfRvCrW3VSv1OWMoIhk=; b=lLQ7neYe2bej+keUZvl+qA5fw8421v9Kv6cs/TsDOHbq441h2p5j93eKUUeamZstGI BoJNdQweknBEE9tCfgKPIy9WsqFyHryxiXKlPcwgfNJogtuj5w2o18xqgYdENfxwocl7 +905T84DHc6wHCQ6iNclbubkmuIsYxewswMmksqq9nqatpyvojw3ys5mtDEhaxFiK67l Zwq7WTEfV1a8KGOkyx2cKp68tR5A8DarCRk3VxNV52L1ih837PxNq7lt4bR/ZRPF1elH tPv+rJOV2xTLbMTMFbKyqKjNR4uB7mi1Uhiz+Hr6jRJ+vukV0ff9qE+3M9gStho+lJ2P WkiA== X-Gm-Message-State: AOAM533O9lwpNJVKmGiFFVUaVqv3lXdABG1RIRtMhPZnFtB30Ot0DhPR YgUP88OpnYfshhhBId8I9w== X-Google-Smtp-Source: ABdhPJwVkq10fOJ3f6j946OdxDX/wCFWm8z6hMh+8f24Q5aunO2lKzUeMK9w3aFhxFYnHljIP6WA4A== X-Received: by 2002:a05:6830:154a:: with SMTP id l10mr16657470otp.97.1631652487422; Tue, 14 Sep 2021 13:48:07 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id y14sm2883236oti.69.2021.09.14.13.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 13:48:06 -0700 (PDT) From: Rob Herring To: Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar Cc: Catalin Marinas , Arnaldo Carvalho de Melo , Jiri Olsa , Kan Liang , Ian Rogers , Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , Vince Weaver , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 5/5] Documentation: arm64: Document PMU counters access from userspace Date: Tue, 14 Sep 2021 15:48:00 -0500 Message-Id: <20210914204800.3945732-6-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210914204800.3945732-1-robh@kernel.org> References: <20210914204800.3945732-1-robh@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Raphael Gault Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v10: - Add details on perf_user_access sysctl v9: - No change v8: - Reword that config1:1 must always be set to request user access v7: - Merge into existing arm64 perf.rst v6: - Update the chained event section with attr.config1 details v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/perf.rst | 73 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d385..47980c9058e3 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,71 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counters, the global sysctl +kernel/perf_user_access must first be enabled: + +.. code-block:: sh + + echo 1 > /proc/sys/kernel/perf_user_access + +It is necessary to open the event using the perf tool interface with config1:1 +attr bit set: the sys_perf_event_open syscall returns a fd which can +subsequently be used with the mmap syscall in order to retrieve a page of memory +containing information about the event. The PMU driver uses this page to expose +to the user the hardware counter's index and other necessary data. Using this +index enables the user to access the PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and 64-bit counters +---------------------------------------- +Chained events are not supported in conjunction with userspace counter +access. If a 64-bit counter is requested (attr.config1:0) with userspace +access (attr.config1:1 set), then counter chaining will be disabled. The +'pmc_width' in the user page will indicate the actual width of the +counter which could be only 32-bits depending on the event and PMU +features. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-22.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C97C433F5 for ; Tue, 14 Sep 2021 20:51:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5746260F4C for ; Tue, 14 Sep 2021 20:51:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5746260F4C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jI9lQ7B/0r9pkxw2m4g4TxckYgtqwpvOlk1nY/w2qzQ=; b=LaH74Hcf8K/MqK EXzaHGDuysmR1umXMmnCwlLQpsKc3Ge0D+baxjay0p+9wUKKuXs2bVlLhW6id3Pu8bXBtYUU6zgpT HnRMqkai9tuFxSH1IWtwp4JJErMMt9EjPX8vRegP43O7LxGnps8BIZW3gcd475JZ+5jrP+qh6TXE+ 0OvFy0IXjZSmfUBNW1/QbyM0v/ezrp+aXicFXfYIS0i7tiOegUAPejLBD4IchjvtFmVbsedYDrL12 JzKsNtv+36iGf0uT1ArOo2DM6R+KLnZ5/Po4u1tzpgeavfKxQBWkF9dNxuAjRPP3RLz0V29GF3D1v NLSuUAFnLvubsQPob2bA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mQFMg-0073fg-QS; Tue, 14 Sep 2021 20:49:15 +0000 Received: from mail-ot1-f52.google.com ([209.85.210.52]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mQFLm-0073GG-59 for linux-arm-kernel@lists.infradead.org; Tue, 14 Sep 2021 20:48:21 +0000 Received: by mail-ot1-f52.google.com with SMTP id m7-20020a9d4c87000000b0051875f56b95so400552otf.6 for ; Tue, 14 Sep 2021 13:48:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hfnaBiDsLPqKzOMV5CVhITztcfRvCrW3VSv1OWMoIhk=; b=COt9A7y/gPhGwmEcngir7s184gSkHzxVbLAYY1fkEhFVoBROyuraANulvQKhEe7uuW PKn6jzS0QLChj4HLfpO9OPrTezPVLblJMavARxq8WuLkHkc/LRdhl2gZjGhkJLvqO9xF uoABdn2YKSZqlC2a0514MleVPxUdw+vJyXvJPz32vKzQtdDZQWydK9wiEOG4P+CKA3gb Jw2EquMij7BY2stW0Y8+zfNEkWeqqAOmRjGOdZLZIC65UcuRtYca2yKfpQmJ6vMQFNra JXZWMclMrO7kY3eujvKMxVUnWA7K8pPMKfAKgSy1BScacTf+GAr/2vDR2yimYvQsjKKL 4lnQ== X-Gm-Message-State: AOAM530NR+6RWjsYINDgbt+mdB31wAzziIVAg+qz3Fthw6xLqC3fN/Om RbnOk3TgUfG0XTOHd/ZMTg== X-Google-Smtp-Source: ABdhPJwVkq10fOJ3f6j946OdxDX/wCFWm8z6hMh+8f24Q5aunO2lKzUeMK9w3aFhxFYnHljIP6WA4A== X-Received: by 2002:a05:6830:154a:: with SMTP id l10mr16657470otp.97.1631652487422; Tue, 14 Sep 2021 13:48:07 -0700 (PDT) Received: from xps15.herring.priv (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.googlemail.com with ESMTPSA id y14sm2883236oti.69.2021.09.14.13.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 13:48:06 -0700 (PDT) From: Rob Herring To: Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar Cc: Catalin Marinas , Arnaldo Carvalho de Melo , Jiri Olsa , Kan Liang , Ian Rogers , Alexander Shishkin , honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , Itaru Kitayama , Vince Weaver , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 5/5] Documentation: arm64: Document PMU counters access from userspace Date: Tue, 14 Sep 2021 15:48:00 -0500 Message-Id: <20210914204800.3945732-6-robh@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210914204800.3945732-1-robh@kernel.org> References: <20210914204800.3945732-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210914_134818_317103_9CA3E4F3 X-CRM114-Status: GOOD ( 24.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault Add documentation to describe the access to the pmu hardware counters from userspace. Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v10: - Add details on perf_user_access sysctl v9: - No change v8: - Reword that config1:1 must always be set to request user access v7: - Merge into existing arm64 perf.rst v6: - Update the chained event section with attr.config1 details v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/perf.rst | 73 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/perf.rst b/Documentation/arm64/perf.rst index b567f177d385..47980c9058e3 100644 --- a/Documentation/arm64/perf.rst +++ b/Documentation/arm64/perf.rst @@ -2,7 +2,10 @@ .. _perf_index: -===================== +==== +Perf +==== + Perf Event Attributes ===================== @@ -88,3 +91,71 @@ exclude_host. However when using !exclude_hv there is a small blackout window at the guest entry/exit where host events are not captured. On VHE systems there are no blackout windows. + +Perf Userspace PMU Hardware Counter Access +========================================== + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counters, the global sysctl +kernel/perf_user_access must first be enabled: + +.. code-block:: sh + + echo 1 > /proc/sys/kernel/perf_user_access + +It is necessary to open the event using the perf tool interface with config1:1 +attr bit set: the sys_perf_event_open syscall returns a fd which can +subsequently be used with the mmap syscall in order to retrieve a page of memory +containing information about the event. The PMU driver uses this page to expose +to the user the hardware counter's index and other necessary data. Using this +index enables the user to access the PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events and 64-bit counters +---------------------------------------- +Chained events are not supported in conjunction with userspace counter +access. If a 64-bit counter is requested (attr.config1:0) with userspace +access (attr.config1:1 set), then counter chaining will be disabled. The +'pmc_width' in the user page will indicate the actual width of the +counter which could be only 32-bits depending on the event and PMU +features. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c +.. _tools/lib/perf/tests/test-evsel.c: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel