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* [Intel-gfx] [PATCH v2 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation
@ 2021-09-14 21:25 José Roberto de Souza
  2021-09-14 21:25 ` [Intel-gfx] [PATCH v2 2/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
                   ` (9 more replies)
  0 siblings, 10 replies; 25+ messages in thread
From: José Roberto de Souza @ 2021-09-14 21:25 UTC (permalink / raw)
  To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza

As the SU_REGION_START begins at 0, the SU_REGION_END should be number
of lines - 1.

BSpec: 50424
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3f6fb7d67f84d..36816abb3bcc0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1501,7 +1501,7 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
 
 	if (IS_ALDERLAKE_P(dev_priv)) {
 		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
-		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2);
+		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
 	} else {
 		drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
 
-- 
2.33.0


^ permalink raw reply related	[flat|nested] 25+ messages in thread

end of thread, other threads:[~2021-09-22 15:51 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-14 21:25 [Intel-gfx] [PATCH v2 1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation José Roberto de Souza
2021-09-14 21:25 ` [Intel-gfx] [PATCH v2 2/5] drm/i915/display: Wait at least 2 frames before selective update José Roberto de Souza
2021-09-14 21:25 ` [Intel-gfx] [PATCH v2 3/5] drm/i915/display: Workaround cursor left overs with PSR2 selective fetch enabled José Roberto de Souza
2021-09-15 14:58   ` Ville Syrjälä
2021-09-15 18:18     ` Souza, Jose
2021-09-16 13:17       ` Ville Syrjälä
2021-09-16 17:09         ` Souza, Jose
2021-09-17 13:04           ` Ville Syrjälä
2021-09-17 17:02             ` Souza, Jose
2021-09-17 17:49               ` Ville Syrjälä
2021-09-17 21:33                 ` Souza, Jose
2021-09-21 13:35                   ` Ville Syrjälä
2021-09-21 22:37                     ` Souza, Jose
2021-09-22 13:41                       ` Ville Syrjälä
2021-09-22 15:51                         ` Souza, Jose
2021-09-14 21:25 ` [Intel-gfx] [PATCH v2 4/5] drm/i915/display/psr: Use drm damage helpers to calculate plane damaged area José Roberto de Souza
2021-09-14 21:25 ` [Intel-gfx] [PATCH v2 5/5] drm/i915/display/adlp: Add new PSR2 workarounds José Roberto de Souza
2021-09-15 14:20   ` Gwan-gyeong Mun
2021-09-14 22:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation Patchwork
2021-09-15 19:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev2) Patchwork
2021-09-15 20:33 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev3) Patchwork
2021-09-16 22:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev4) Patchwork
2021-09-17  0:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/5] drm/i915/display/adlp: Fix PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR calculation (rev5) Patchwork
2021-09-17  4:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-17 17:52   ` Souza, Jose

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