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[95.92.181.29]) by smtp.gmail.com with ESMTPSA id s24sm583246wmh.34.2021.09.15.10.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Sep 2021 10:54:44 -0700 (PDT) Date: Wed, 15 Sep 2021 18:54:37 +0100 From: Melissa Wen To: Iago Toral Quiroga Cc: dri-devel@lists.freedesktop.org, mwen@igalia.com Subject: Re: [PATCH v2] drm/v3d: fix wait for TMU write combiner flush Message-ID: <20210915175437.g6mepp3blbbps6gb@smtp.gmail.com> References: <20210915085707.7ph5sx4nnetb2mbn@mail.igalia.com> <20210915100507.3945-1-itoral@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210915100507.3945-1-itoral@igalia.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 09/15, Iago Toral Quiroga wrote: > The hardware sets the TMUWCF bit back to 0 when the TMU write > combiner flush completes so we should be checking for that instead > of the L2TFLS bit. > > v2 (Melissa Wen): > - Add Signed-off-by and Fixes tags. > - Change the error message for the timeout to be more clear. > > Fixes spurious Vulkan CTS failures in: > dEQP-VK.binding_model.descriptorset_random.* > > Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch") > Signed-off-by: Iago Toral Quiroga > Reviewed-by: Melissa Wen Applied to drm-misc-next. Thanks, Melissa > --- > drivers/gpu/drm/v3d/v3d_gem.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c > index a3529809d547..1953706bdaeb 100644 > --- a/drivers/gpu/drm/v3d/v3d_gem.c > +++ b/drivers/gpu/drm/v3d/v3d_gem.c > @@ -197,8 +197,8 @@ v3d_clean_caches(struct v3d_dev *v3d) > > V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); > if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & > - V3D_L2TCACTL_L2TFLS), 100)) { > - DRM_ERROR("Timeout waiting for L1T write combiner flush\n"); > + V3D_L2TCACTL_TMUWCF), 100)) { > + DRM_ERROR("Timeout waiting for TMU write combiner flush\n"); > } > > mutex_lock(&v3d->cache_clean_lock); > -- > 2.25.1 >