From: Tong Ho <tong.ho@xilinx.com>
To: <qemu-arm@nongnu.org>
Cc: edgar.iglesias@gmail.com, alistair@alistair23.me,
tong.ho@xilinx.com, qemu-devel@nongnu.org,
peter.maydell@linaro.org
Subject: [PATCH v3 6/9] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
Date: Thu, 16 Sep 2021 22:23:57 -0700 [thread overview]
Message-ID: <20210917052400.1249094-7-tong.ho@xilinx.com> (raw)
In-Reply-To: <20210917052400.1249094-1-tong.ho@xilinx.com>
Connect the support for Versal eFUSE one-time field-programmable
bit array.
The command argument:
-drive if=pflash,index=1,...
Can be used to optionally connect the bit array to a
backend storage, such that field-programmed values
in one invocation can be made available to next
invocation.
The backend storage must be a seekable binary file, and
its size must be 3072 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
---
hw/arm/Kconfig | 1 +
hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++
hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++
include/hw/arm/xlnx-versal.h | 10 +++++++
4 files changed, 102 insertions(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index f92fb9e568..9edc05782d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -382,6 +382,7 @@ config XLNX_VERSAL
select XLNX_ZYNQMP
select OR_IRQ
select XLNX_BBRAM
+ select XLNX_EFUSE_VERSAL
config NPCM7XX
bool
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index e1c5ead475..d2f55e29b6 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -376,6 +376,41 @@ static void fdt_add_bbram_node(VersalVirt *s)
g_free(name);
}
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
+{
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
+ const char interrupt_names[] = "pmc_efuse";
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
+
+ qemu_fdt_add_subnode(s->fdt, name);
+
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+ interrupt_names, sizeof(interrupt_names));
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_PMC_EFUSE_CTRL,
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+ g_free(name);
+}
+
+static void fdt_add_efuse_cache_node(VersalVirt *s)
+{
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x",
+ MM_PMC_EFUSE_CACHE);
+
+ qemu_fdt_add_subnode(s->fdt, name);
+
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_PMC_EFUSE_CACHE,
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+ g_free(name);
+}
+
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
{
Error *err = NULL;
@@ -542,6 +577,18 @@ static void bbram_attach_drive(XlnxBBRam *dev)
}
}
+static void efuse_attach_drive(XlnxEFuse *dev)
+{
+ DriveInfo *dinfo;
+ BlockBackend *blk;
+
+ dinfo = drive_get_by_index(IF_PFLASH, 1);
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
+ if (blk) {
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
+ }
+}
+
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
{
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
@@ -603,6 +650,8 @@ static void versal_virt_init(MachineState *machine)
fdt_add_sd_nodes(s);
fdt_add_rtc_node(s);
fdt_add_bbram_node(s);
+ fdt_add_efuse_ctrl_node(s);
+ fdt_add_efuse_cache_node(s);
fdt_add_cpu_nodes(s, psci_conduit);
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
@@ -615,6 +664,9 @@ static void versal_virt_init(MachineState *machine)
/* Attach bbram backend, if given */
bbram_attach_drive(&s->soc.pmc.bbram);
+ /* Attach efuse backend, if given */
+ efuse_attach_drive(&s->soc.pmc.efuse);
+
/* Plugin SD cards. */
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 23451ae012..b2705b6925 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -331,6 +331,44 @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
}
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
+{
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
+
+ object_property_set_link(OBJECT(part), "efuse",
+ OBJECT(&s->pmc.efuse), &error_abort);
+
+ sysbus_realize(part, &error_abort);
+ memory_region_add_subregion(&s->mr_ps, base,
+ sysbus_mmio_get_region(part, 0));
+}
+
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
+{
+ Object *bits = OBJECT(&s->pmc.efuse);
+ Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
+ Object *cache = OBJECT(&s->pmc.efuse_cache);
+
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
+
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
+
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
+ sizeof(s->pmc.efuse),
+ TYPE_XLNX_EFUSE, &error_abort,
+ "efuse-nr", "3",
+ "efuse-size", "8192",
+ NULL);
+
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
@@ -420,6 +458,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_rtc(s, pic);
versal_create_xrams(s, pic);
versal_create_bbram(s, pic);
+ versal_create_efuse(s, pic);
versal_map_ddr(s);
versal_unimp(s);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 1cac613338..895ba12c61 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -25,6 +25,7 @@
#include "hw/usb/xlnx-usb-subsystem.h"
#include "hw/misc/xlnx-versal-xramc.h"
#include "hw/nvram/xlnx-bbram.h"
+#include "hw/nvram/xlnx-versal-efuse.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -81,6 +82,9 @@ struct Versal {
XlnxZynqMPRTC rtc;
XlnxBBRam bbram;
+ XlnxEFuse efuse;
+ XlnxVersalEFuseCtrl efuse_ctrl;
+ XlnxVersalEFuseCache efuse_cache;
} pmc;
struct {
@@ -110,6 +114,7 @@ struct Versal {
#define VERSAL_BBRAM_APB_IRQ_0 121
#define VERSAL_RTC_APB_ERR_IRQ 121
#define VERSAL_SD0_IRQ_0 126
+#define VERSAL_EFUSE_IRQ 139
#define VERSAL_RTC_ALARM_IRQ 142
#define VERSAL_RTC_SECONDS_IRQ 143
@@ -177,6 +182,11 @@ struct Versal {
#define MM_PMC_SD0_SIZE 0x10000
#define MM_PMC_BBRAM_CTRL 0xf11f0000
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
+#define MM_PMC_EFUSE_CTRL 0xf1240000
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
+#define MM_PMC_EFUSE_CACHE 0xf1250000
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
+
#define MM_PMC_CRP 0xf1260000U
#define MM_PMC_CRP_SIZE 0x10000
#define MM_PMC_RTC 0xf12a0000
--
2.25.1
next prev parent reply other threads:[~2021-09-17 5:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 5:23 [PATCH v3 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Tong Ho
2021-09-17 5:23 ` [PATCH v3 1/9] hw/nvram: Introduce Xilinx eFuse QOM Tong Ho
2021-09-17 5:23 ` [PATCH v3 2/9] hw/nvram: Introduce Xilinx Versal eFuse device Tong Ho
2021-09-17 5:23 ` [PATCH v3 3/9] hw/nvram: Introduce Xilinx ZynqMP " Tong Ho
2021-09-17 5:23 ` [PATCH v3 4/9] hw/nvram: Introduce Xilinx battery-backed ram Tong Ho
2021-09-17 5:23 ` [PATCH v3 5/9] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device Tong Ho
2021-09-17 5:23 ` Tong Ho [this message]
2021-09-17 5:23 ` [PATCH v3 7/9] hw/arm: xlnx-zcu102: " Tong Ho
2021-09-17 5:23 ` [PATCH v3 8/9] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device Tong Ho
2021-09-17 5:24 ` [PATCH v3 9/9] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage Tong Ho
2021-09-27 11:07 ` [PATCH v3 0/9] hw/nvram: hw/arm: Introduce Xilinx eFUSE and BBRAM Peter Maydell
2021-10-02 10:28 ` Peter Maydell
2021-10-04 15:54 ` Tong Ho
2021-11-01 11:22 ` Peter Maydell
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