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From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>
Cc: <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v3 13/17] clk: at91: sama7g5: remove prescaler part of master clock
Date: Fri, 17 Sep 2021 15:06:38 +0300	[thread overview]
Message-ID: <20210917120642.8993-14-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210917120642.8993-1-claudiu.beznea@microchip.com>

On SAMA7G5 the prescaler part of master clock has been implemented as a
changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
been discovered that in some conditions the PMC_SR.MCKRDY is not rising
but the rate it provides it's stable. The workaround is to add a timeout
when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
will be removed from Linux clock tree as all the frequencies for CPU could
be obtained from PLL and also there will be less overhead when changing
frequency via DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/sama7g5.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index c72886681d74..aaa5769a8df1 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -1021,16 +1021,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 	}
 
 	parent_names[0] = "cpupll_divpmcck";
-	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
-					   &mck0_layout, &mck0_characteristics,
-					   &pmc_mck0_lock,
-					   CLK_SET_RATE_PARENT, 0);
-	if (IS_ERR(hw))
-		goto err_free;
-
-	sama7g5_pmc->chws[PMC_CPU] = hw;
-
-	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
+	hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
 					  &mck0_layout, &mck0_characteristics,
 					  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
 	if (IS_ERR(hw))
-- 
2.25.1


WARNING: multiple messages have this Message-ID
From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>
Cc: <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v3 13/17] clk: at91: sama7g5: remove prescaler part of master clock
Date: Fri, 17 Sep 2021 15:06:38 +0300	[thread overview]
Message-ID: <20210917120642.8993-14-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210917120642.8993-1-claudiu.beznea@microchip.com>

On SAMA7G5 the prescaler part of master clock has been implemented as a
changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit
must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is
done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has
been discovered that in some conditions the PMC_SR.MCKRDY is not rising
but the rate it provides it's stable. The workaround is to add a timeout
when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler
will be removed from Linux clock tree as all the frequencies for CPU could
be obtained from PLL and also there will be less overhead when changing
frequency via DVFS.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/clk/at91/sama7g5.c | 11 +----------
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index c72886681d74..aaa5769a8df1 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -1021,16 +1021,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 	}
 
 	parent_names[0] = "cpupll_divpmcck";
-	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
-					   &mck0_layout, &mck0_characteristics,
-					   &pmc_mck0_lock,
-					   CLK_SET_RATE_PARENT, 0);
-	if (IS_ERR(hw))
-		goto err_free;
-
-	sama7g5_pmc->chws[PMC_CPU] = hw;
-
-	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
+	hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
 					  &mck0_layout, &mck0_characteristics,
 					  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
 	if (IS_ERR(hw))
-- 
2.25.1


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  parent reply	other threads:[~2021-09-17 12:08 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-17 12:06 [PATCH v3 00/17] clk: at91: updates for power management and dvfs Claudiu Beznea
2021-09-17 12:06 ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 01/17] clk: at91: re-factor clocks suspend/resume Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:20   ` Claudiu.Beznea
2021-09-17 12:20     ` Claudiu.Beznea
2021-09-17 12:06 ` [PATCH v3 02/17] clk: at91: pmc: execute suspend/resume only for backup mode Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 03/17] clk: at91: sama7g5: add securam's peripheral clock Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 04/17] clk: at91: clk-master: add register definition for sama7g5's master clock Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 05/17] clk: at91: clk-master: improve readability by using local variables Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 06/17] clk: at91: pmc: add sama7g5 to the list of available pmcs Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 07/17] clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 08/17] clk: at91: clk-master: check if div or pres is zero Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 09/17] clk: at91: clk-master: mask mckr against layout->mask Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 10/17] clk: at91: clk-master: fix prescaler logic Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 11/17] clk: at91: clk-sam9x60-pll: add notifier for div part of PLL Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 12/17] clk: at91: clk-master: add notifier for divider Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` Claudiu Beznea [this message]
2021-09-17 12:06   ` [PATCH v3 13/17] clk: at91: sama7g5: remove prescaler part of master clock Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 14/17] clk: at91: sama7g5: set low limit for mck0 at 32KHz Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 15/17] clk: use clk_core_get_rate_recalc() in clk_rate_get() Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 16/17] clk: remove extra empty line Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea
2021-09-17 12:06 ` [PATCH v3 17/17] clk: do not initialize ret Claudiu Beznea
2021-09-17 12:06   ` Claudiu Beznea

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