On Tue, Sep 07, 2021 at 05:16:54PM -0500, Dave Gerlach wrote:

> From: Suman Anna <s-anna@ti.com>
> 
> The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
> divisors to generate the final FOUTPOSTDIV clock. These are in sequence
> with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
> has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
> opposite of the actual implementation. Fix the data by simply adjusting
> the register bit-shifts.
> 
> The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
> register values, fix these as well.
> 
> Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom