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From: Mark Kettenis <kettenis@openbsd.org>
To: u-boot@lists.denx.de
Cc: "Mark Kettenis" <kettenis@openbsd.org>,
	"Oliver Graute" <oliver.graute@kococonnector.com>,
	"Leo Yu-Chi Liang" <ycliang@andestech.com>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Stephan Gerhold" <stephan@gerhold.net>,
	"Tianrui Wei" <tianrui-wei@outlook.com>,
	"Heinrich Schuchardt" <xypron.glpk@gmx.de>,
	"Simon Glass" <sjg@chromium.org>,
	"Asherah Connor" <ashe@kivikakk.ee>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Wasim Khan" <wasim.khan@nxp.com>,
	"Igor Opaniuk" <igor.opaniuk@foundries.io>,
	"Ye Li" <ye.li@nxp.com>, "Stefan Roese" <sr@denx.de>,
	"Vabhav Sharma" <vabhav.sharma@nxp.com>,
	"Marek Behún" <marek.behun@nic.cz>,
	"Weijie Gao" <weijie.gao@mediatek.com>,
	"AKASHI Takahiro" <takahiro.akashi@linaro.org>,
	"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
	"Pratyush Yadav" <p.yadav@ti.com>
Subject: [PATCH 4/5] arm: dts: apple: Add preliminary device trees
Date: Sat, 18 Sep 2021 15:54:25 +0200	[thread overview]
Message-ID: <20210918135437.36667-5-kettenis@openbsd.org> (raw)
In-Reply-To: <20210918135437.36667-1-kettenis@openbsd.org>

Add preliminary device trees for the Apple M1 mini (2020) and
Apple M1 Macbook Pro 13" (2020).  Device tree bindings for
the Apple M1 SoC are still being formalized and these device
trees will be synchronized with the Linux kernel as needed.

These device trees are provided as a reference only as U-Boot
uses the device tree passed by the m1n1 bootloader.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
---
 arch/arm/dts/t8103-j274.dts                   | 135 +++++
 arch/arm/dts/t8103-j293.dts                   |  97 ++++
 arch/arm/dts/t8103.dtsi                       | 506 ++++++++++++++++++
 .../interrupt-controller/apple-aic.h          |  15 +
 include/dt-bindings/pinctrl/apple.h           |  13 +
 include/dt-bindings/spmi/spmi.h               |  10 +
 6 files changed, 776 insertions(+)
 create mode 100644 arch/arm/dts/t8103-j274.dts
 create mode 100644 arch/arm/dts/t8103-j293.dts
 create mode 100644 arch/arm/dts/t8103.dtsi
 create mode 100644 include/dt-bindings/interrupt-controller/apple-aic.h
 create mode 100644 include/dt-bindings/pinctrl/apple.h
 create mode 100644 include/dt-bindings/spmi/spmi.h

diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts
new file mode 100644
index 0000000000..aef1ae29b6
--- /dev/null
+++ b/arch/arm/dts/t8103-j274.dts
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple Mac mini (M1, 2020)
+ *
+ * target-type: J274
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t8103.dtsi"
+
+/ {
+	compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
+	model = "Apple Mac mini (M1, 2020)";
+
+	aliases {
+		serial0 = &serial0;
+		ethernet0 = &eth0;
+		wifi0 = &wifi0;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		stdout-path = "serial0";
+
+		framebuffer0: framebuffer@0 {
+			compatible = "apple,simple-framebuffer", "simple-framebuffer";
+			reg = <0 0 0 0>; /* To be filled by loader */
+			/* Format properties will be added by loader */
+			status = "disabled";
+		};
+	};
+
+	memory@800000000 {
+		device_type = "memory";
+		reg = <0x8 0 0x2 0>; /* To be filled by loader */
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&pcie0_dart_0 {
+	status = "okay";
+};
+
+&pcie0_dart_1 {
+	status = "okay";
+};
+
+&pcie0_dart_2 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	pci0: pci@0,0 {
+		device_type = "pci";
+		reg = <0x0 0x0 0x0 0x0 0x0>;
+		pwren-gpios = <&smc 13 0>;
+		reset-gpios = <&pinctrl_ap 152 0>;
+		max-link-speed = <2>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+	};
+
+	pci1: pci@1,0 {
+		device_type = "pci";
+		reg = <0x800 0x0 0x0 0x0 0x0>;
+		reset-gpios = <&pinctrl_ap 153 0>;
+		max-link-speed = <2>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+	};
+
+	pci2: pci@2,0 {
+		device_type = "pci";
+		reg = <0x1000 0x0 0x0 0x0 0x0>;
+		reset-gpios = <&pinctrl_ap 33 0>;
+		max-link-speed = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+	};
+};
+
+&pci0 {
+	wifi0: network@0,0 {
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		local-mac-address = [00 00 00 00 00 00];
+	};
+};
+
+&pci2 {
+	eth0: ethernet@0,0 {
+		reg = <0x30000 0x0 0x0 0x0 0x0>;
+		local-mac-address = [00 00 00 00 00 00];
+	};
+};
+
+&dwc3_0_dart_0 {
+	status = "okay";
+};
+
+&dwc3_0_dart_1 {
+	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
+};
+
+&dwc3_1_dart_0 {
+	status = "okay";
+};
+
+&dwc3_1_dart_1 {
+	status = "okay";
+};
+
+&dwc3_1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/t8103-j293.dts b/arch/arm/dts/t8103-j293.dts
new file mode 100644
index 0000000000..4a22596cf4
--- /dev/null
+++ b/arch/arm/dts/t8103-j293.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple Macbook Pro (M1, 2020)
+ *
+ * target-type: J293
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+/dts-v1/;
+
+#include "t8103.dtsi"
+
+/ {
+	compatible = "apple,j293", "apple,t8103", "apple,arm-platform";
+	model = "Apple Macbook Pro (M1, 2020)";
+
+	aliases {
+		serial0 = &serial0;
+		wifi0 = &wifi0;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		stdout-path = "serial0";
+
+		framebuffer0: framebuffer@0 {
+			compatible = "apple,simple-framebuffer", "simple-framebuffer";
+			reg = <0 0 0 0>; /* To be filled by loader */
+			/* Format properties will be added by loader */
+			status = "disabled";
+		};
+	};
+
+	memory@800000000 {
+		device_type = "memory";
+		reg = <0x8 0 0x2 0>; /* To be filled by loader */
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&pcie0_dart_0 {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	pci0: pci@0,0 {
+		device_type = "pci";
+		reg = <0x0 0x0 0x0 0x0 0x0>;
+		pwren-gpios = <&smc 13 0>;
+		reset-gpios = <&pinctrl_ap 152 0>;
+		max-link-speed = <2>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+	};
+};
+
+&pci0 {
+	wifi0: network@0,0 {
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+		local-mac-address = [00 00 00 00 00 00];
+	};
+};
+
+&dwc3_0_dart_0 {
+	status = "okay";
+};
+
+&dwc3_0_dart_1 {
+	status = "okay";
+};
+
+&dwc3_0 {
+	status = "okay";
+};
+
+&dwc3_1_dart_0 {
+	status = "okay";
+};
+
+&dwc3_1_dart_1 {
+	status = "okay";
+};
+
+&dwc3_1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/t8103.dtsi b/arch/arm/dts/t8103.dtsi
new file mode 100644
index 0000000000..6074fc9080
--- /dev/null
+++ b/arch/arm/dts/t8103.dtsi
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Apple T8103 "M1" SoC
+ *
+ * Other names: H13G, "Tonga"
+ *
+ * Copyright The Asahi Linux Contributors
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/apple-aic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/apple.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	compatible = "apple,t8103", "apple,arm-platform";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "apple,icestorm";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu1: cpu@1 {
+			compatible = "apple,icestorm";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu2: cpu@2 {
+			compatible = "apple,icestorm";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu3: cpu@3 {
+			compatible = "apple,icestorm";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu4: cpu@10100 {
+			compatible = "apple,firestorm";
+			device_type = "cpu";
+			reg = <0x0 0x10100>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu5: cpu@10101 {
+			compatible = "apple,firestorm";
+			device_type = "cpu";
+			reg = <0x0 0x10101>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu6: cpu@10102 {
+			compatible = "apple,firestorm";
+			device_type = "cpu";
+			reg = <0x0 0x10102>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+
+		cpu7: cpu@10103 {
+			compatible = "apple,firestorm";
+			device_type = "cpu";
+			reg = <0x0 0x10103>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0 0>; /* To be filled by loader */
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&aic>;
+		interrupt-names = "hyp-phys", "hyp-virt", "phys", "virt";
+		interrupts = <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
+			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	clk24: clock-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "clk24";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges;
+		dma-ranges;
+		dma-coherent;
+		nonposted-mmio;
+
+		aic: interrupt-controller@23b100000 {
+			compatible = "apple,t8103-aic", "apple,aic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x2 0x3b100000 0x0 0x8000>;
+		};
+
+		serial0: serial@235200000 {
+			compatible = "apple,s5l-uart";
+			reg = <0x2 0x35200000 0x0 0x1000>;
+			reg-io-width = <4>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			 * TODO: figure out the clocking properly, there may
+			 * be a third selectable clock.
+			 */
+			clocks = <&clk24>, <&clk24>;
+			clock-names = "uart", "clk_uart_baud0";
+			status = "disabled";
+		};
+
+		gpio_clk: clock@23b700130 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b700130 0x0 0x8>;
+			#clock-cells = <0>;
+		};
+
+		pinctrl_ap: pinctrl@23c100000 {
+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+			reg = <0x2 0x3c100000 0x0 0x100000>;
+			clocks = <&gpio_clk>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_ap 0 0 212>;
+
+			interrupt-controller;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;
+
+			i2c0_pins: i2c0_pins {
+				pinmux = <APPLE_PINMUX(188, 1)>,
+					 <APPLE_PINMUX(192, 1)>;
+			};
+
+			pcie_pins: pcie-pins {
+				pinmux = <APPLE_PINMUX(150, 1)>,
+				         <APPLE_PINMUX(151, 1)>,
+					 <APPLE_PINMUX(32, 1)>;
+			};
+		};
+
+		pinctrl_aop: pinctrl@24a820000 {
+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+			reg = <0x2 0x4a820000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_aop 0 0 42>;
+
+			interrupt-controller;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_nub: pinctrl@23d1f0000 {
+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+			reg = <0x2 0x3d1f0000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_nub 0 0 23>;
+
+			interrupt-controller;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_smc: pinctrl@23e820000 {
+			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+			reg = <0x2 0x3e820000 0x0 0x4000>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl_smc 0 0 16>;
+
+			interrupt-controller;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sio_busif_clk: clock@23b7001c0 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7001c0 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&clk24>;
+		};
+
+		sio_clk: clock@23b7001c8 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7001c8 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&sio_busif_clk>;
+		};
+
+		i2c0_clk: clock@23b7001f0 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7001f0 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&sio_clk>;
+		};
+
+		i2c0: i2c@20a110000 {
+			compatible = "apple,i2c-v0";
+			reg = <0x2 0x35010000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&i2c0_clk>;
+			pinctrl-0 = <&i2c0_pins>;
+			pinctrl-names = "default";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			hpm0: hpm@38 {
+				compatible = "ti,tps6598x";
+				reg = <0x38>;
+			};
+
+			hpm1: hpm@3f {
+				compatible = "ti,tps6598x";
+				reg = <0x3f>;
+			};
+                };
+
+		imx_clk: clock@23b7001b8 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7001b8 0x0 0x8>;
+			#clock-cells = <0>;
+		};
+
+		pcie_aux_clk: clock@23b700348 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b700348 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&imx_clk>;
+		};
+
+		pcie_core_clk: clock@23b7003e8 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7003e8 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&pcie_aux_clk>;
+		};
+
+		pcie_ref_clk: clock@23b7001a0 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7001a0 0x0 0x8>;
+			#clock-cells = <0>;
+		};
+
+		ans_clk: clock@23b7003f0 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b7003f0 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&pcie_aux_clk>;
+		};
+
+		ans_st_clk: clock@23b700418 {
+			compatible = "apple,pmgr-clk-gate";
+			reg = <0x2 0x3b700418 0x0 0x8>;
+			#clock-cells = <0>;
+			clocks = <&ans_clk>;
+		};
+
+		ans_mbox: mbox@277400000 {
+			compatible = "apple,iop-mailbox-m1";
+			reg = <0x2 0x77400000 0x0 0x20000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ans_st_clk>;
+			#mbox-cells = <1>;
+			endpoints = <32>;
+		};
+
+		ans@27bcc0000 {
+			compatible = "apple,nvme-m1";
+			reg = <0x2 0x7bcc0000 0x0 0x40000>,
+			      <0x2 0x7bc50000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ans_st_clk>;
+			mboxes = <&ans_mbox 32>;
+		};
+
+		pcie0_dart_0: iommu@681008000 {
+			compatible = "apple,t8103-dart", "apple,dart-m1";
+			reg = <0x6 0x81008000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		pcie0_dart_1: iommu@682008000 {
+			compatible = "apple,t8103-dart", "apple,dart-m1";
+			reg = <0x6 0x82008000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		pcie0_dart_2: iommu@683008000 {
+			compatible = "apple,t8103-dart", "apple,dart-m1";
+			reg = <0x6 0x83008000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		smc_mbox: mbox@23e400000 {
+			compatible = "apple,iop-mailbox-m1";
+			reg = <0x2 0x3e400000 0x0 0x20000>;
+			#mbox-cells = <1>;
+			endpoints = <32>;
+		};
+
+		smc: smc@23e050000 {
+			compatible = "apple,smc-m1";
+			reg = <0x2 0x3e050000 0x0 0x4000>;
+			mboxes = <&smc_mbox 32>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-13 = <0x00800000>;
+		};
+
+		pcie0: pcie@690000000 {
+			compatible = "apple,t8103-pcie", "apple,pcie";
+
+			reg = <0x6 0x90000000 0x0 0x1000000>,
+			      <0x6 0x80000000 0x0 0x4000>,
+			      <0x6 0x81000000 0x0 0x8000>,
+			      <0x6 0x82000000 0x0 0x8000>,
+			      <0x6 0x83000000 0x0 0x8000>;
+			reg-names = "config", "rc", "port0", "port1", "port2";
+
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
+				     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;
+
+			msi-controller;
+			msi-parent = <&pcie0>;
+			msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;
+
+			iommu-map = <0x100 &pcie0_dart_0 1 1>,
+				    <0x200 &pcie0_dart_1 1 1>,
+				    <0x300 &pcie0_dart_2 1 1>;
+			iommu-map-mask = <0xff00>;
+
+			bus-range = <0 3>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000
+			          0x0 0x20000000>,
+				 <0x02000000 0x0 0xc0000000 0x6 0xc0000000
+				  0x0 0x40000000>;
+
+			clocks = <&pcie_core_clk>, <&pcie_aux_clk>,
+				 <&pcie_ref_clk>;
+			pinctrl-0 = <&pcie_pins>;
+			pinctrl-names = "default";
+
+			device_type = "pci";
+			status = "disabled";
+		};
+
+		dwc3_0_dart_0: iommu@382f00000 {
+			compatible = "apple,t8103-dart";
+			reg = <0x3 0x82f00000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		dwc3_0_dart_1: iommu@382f80000 {
+			compatible = "apple,t8103-dart";
+			reg = <0x3 0x82f80000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		dwc3_0: usb@382280000{
+			compatible = "snps,dwc3";
+			reg = <0x3 0x82280000 0x0 0x100000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>;
+			status = "disabled";
+		};
+
+		dwc3_1_dart_0: iommu@502f00000 {
+			compatible = "apple,t8103-dart";
+			reg = <0x5 0x02f00000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		dwc3_1_dart_1: iommu@502f80000 {
+			compatible = "apple,t8103-dart";
+			reg = <0x5 0x02f80000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>;
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
+		dwc3_1: usb@502280000{
+			compatible = "snps,dwc3";
+			reg = <0x5 0x02280000 0x0 0x100000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>;
+			status = "disabled";
+		};
+
+		reboot@23d2b0000 {
+			compatible = "apple,reboot-v0";
+			reg = <0x2 0x3d2b0000 0x0 0x4000>;
+		};
+
+		spi@23510c000 {
+			compatible = "apple,t8103-spi", "apple,spi";
+			reg = <0x2 0x3510c000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>;
+			cs-gpios = <&pinctrl_ap 49 GPIO_ACTIVE_HIGH>;
+		};
+
+		spmi@23d0d8000 {
+			compatible = "apple,t8103-spmi", "apple,spmi";
+			reg = <0x2 0x3d0d9300 0x0 0x100>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+
+			pmu@f {
+				compatible = "apple,sera-pmu";
+				reg = <0xf SPMI_USID>;
+			};
+		};
+	};
+};
diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h
new file mode 100644
index 0000000000..9ac56a7e6d
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/apple-aic.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define AIC_IRQ	0
+#define AIC_FIQ	1
+
+#define AIC_TMR_HV_PHYS		0
+#define AIC_TMR_HV_VIRT		1
+#define AIC_TMR_GUEST_PHYS	2
+#define AIC_TMR_GUEST_VIRT	3
+
+#endif
diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h
new file mode 100644
index 0000000000..ea0a6f4665
--- /dev/null
+++ b/include/dt-bindings/pinctrl/apple.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * This header provides constants for Apple pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_APPLE_H
+#define _DT_BINDINGS_PINCTRL_APPLE_H
+
+#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
+#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
+#define APPLE_FUNC(pinmux) ((pinmux) >> 16)
+
+#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */
diff --git a/include/dt-bindings/spmi/spmi.h b/include/dt-bindings/spmi/spmi.h
new file mode 100644
index 0000000000..ad4a43481d
--- /dev/null
+++ b/include/dt-bindings/spmi/spmi.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ */
+#ifndef __DT_BINDINGS_SPMI_H
+#define __DT_BINDINGS_SPMI_H
+
+#define SPMI_USID	0
+#define SPMI_GSID	1
+
+#endif
-- 
2.33.0


  parent reply	other threads:[~2021-09-18 13:56 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-18 13:54 [PATCH 0/5] Apple M1 Support Mark Kettenis
2021-09-18 13:54 ` [PATCH 1/5] arm: apple: Add initial support for Apple's M1 SoC Mark Kettenis
2021-09-19  1:04   ` Bin Meng
2021-09-19  1:17     ` Bin Meng
2021-09-19 20:33       ` Mark Kettenis
2021-09-21 12:42         ` Tom Rini
2021-09-21 15:53           ` Bin Meng
2021-09-21 16:04             ` Tom Rini
2021-09-21 16:08             ` Mark Kettenis
2021-09-25 13:27               ` Simon Glass
2021-09-19 20:05     ` Mark Kettenis
2021-09-20  3:15   ` Simon Glass
2021-09-20  8:49     ` Mark Kettenis
2021-09-21  1:11       ` Simon Glass
2021-09-18 13:54 ` [PATCH 2/5] serial: s5p: Add Apple M1 support Mark Kettenis
2021-09-19  1:11   ` Bin Meng
2021-09-19 20:30     ` Mark Kettenis
2021-09-20  3:15   ` Simon Glass
2021-09-25 13:27     ` Simon Glass
2021-10-02 22:15     ` Mark Kettenis
2021-10-03  2:01       ` Simon Glass
2021-09-18 13:54 ` [PATCH 3/5] misc: Add Apple DART driver Mark Kettenis
2021-09-20  3:16   ` Simon Glass
2021-09-20  8:33     ` Mark Kettenis
2021-09-21  1:11       ` Simon Glass
2021-09-25 13:27         ` Simon Glass
2021-09-26 20:53         ` Mark Kettenis
2021-09-27 20:14           ` Simon Glass
2021-09-18 13:54 ` Mark Kettenis [this message]
2021-09-20  3:16   ` [PATCH 4/5] arm: dts: apple: Add preliminary device trees Simon Glass
2021-09-25 13:27     ` Simon Glass
2021-09-18 13:54 ` [PATCH 5/5] doc: board: apple: Add Apple M1 documentation Mark Kettenis
2021-09-19  1:22   ` Bin Meng
2021-09-20  3:16   ` Simon Glass
2021-09-25 13:27     ` Simon Glass
2021-09-20  8:45   ` Igor Opaniuk
2021-09-25  1:20 ` [PATCH 0/5] Apple M1 Support Simon Glass
2021-09-25  8:11   ` Mark Kettenis
2021-09-25 13:27     ` Simon Glass
2021-09-25 13:52       ` Mark Kettenis
2021-09-25 14:42         ` Simon Glass
2021-09-25 16:45           ` Mark Kettenis
2021-09-26 15:53             ` Simon Glass
2021-09-28  3:46               ` Simon Glass
2021-09-28  7:36                 ` Mark Kettenis
2021-09-28 12:07                   ` Simon Glass

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