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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id h18sm16852001wrb.33.2021.09.20.14.46.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 14:46:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v5 18/31] target/mips: Restrict has_work() handler to sysemu and TCG Date: Mon, 20 Sep 2021 23:44:34 +0200 Message-Id: <20210920214447.2998623-19-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210920214447.2998623-1-f4bug@amsat.org> References: <20210920214447.2998623-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 00e0c55d0e4..3639c03f8ea 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -128,6 +128,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) mips_env_set_pc(&cpu->env, value); } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -172,6 +173,7 @@ static bool mips_cpu_has_work(CPUState *cs) } return has_work; } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #include "cpu-defs.c.inc" @@ -542,6 +544,7 @@ static const struct TCGCPUOps mips_tcg_ops = { .tlb_fill = mips_cpu_tlb_fill, #if !defined(CONFIG_USER_ONLY) + .has_work = mips_cpu_has_work, .cpu_exec_interrupt = mips_cpu_exec_interrupt, .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, @@ -563,7 +566,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; - cc->has_work = mips_cpu_has_work; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->gdb_read_register = mips_cpu_gdb_read_register; -- 2.31.1