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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
	Max Hsu <max.hsu@sifive.com>, Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
Date: Tue, 21 Sep 2021 16:54:05 +1000	[thread overview]
Message-ID: <20210921065412.312381-15-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com>

From: Frank Chang <frank.chang@sifive.com>

Setting Control.claim clears all of the chanel's Next registers.
This is effective only when Control.claim is set from 0 to 1.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/dma/sifive_pdma.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index 9b2ac2017d..d92e27dfdc 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -54,6 +54,13 @@
 #define DMA_EXEC_DST        0x110
 #define DMA_EXEC_SRC        0x118
 
+/*
+ * FU540/FU740 docs are incorrect with NextConfig.wsize/rsize reset values.
+ * The reset values tested on Unleashed/Unmatched boards are 6 instead of 0.
+ */
+#define CONFIG_WRSZ_DEFAULT 6
+#define CONFIG_RDSZ_DEFAULT 6
+
 enum dma_chan_state {
     DMA_CHAN_STATE_IDLE,
     DMA_CHAN_STATE_STARTED,
@@ -221,6 +228,7 @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
 {
     SiFivePDMAState *s = opaque;
     int ch = SIFIVE_PDMA_CHAN_NO(offset);
+    bool claimed;
 
     if (ch >= SIFIVE_PDMA_CHANS) {
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
@@ -231,6 +239,17 @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
     offset &= 0xfff;
     switch (offset) {
     case DMA_CONTROL:
+        claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+
+        if (!claimed && (value & CONTROL_CLAIM)) {
+            /* reset Next* registers */
+            s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) |
+                                      (CONFIG_WRSZ_DEFAULT << CONFIG_WRSZ_SHIFT);
+            s->chan[ch].next_bytes = 0;
+            s->chan[ch].next_dst = 0;
+            s->chan[ch].next_src = 0;
+        }
+
         s->chan[ch].control = value;
 
         if (value & CONTROL_RUN) {
-- 
2.31.1



  parent reply	other threads:[~2021-09-21  7:14 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21  6:53 [PULL v2 00/21] riscv-to-apply queue Alistair Francis
2021-09-21  6:53 ` [PULL v2 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-21  6:53 ` [PULL v2 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-21  6:53 ` [PULL v2 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-21  6:53 ` [PULL v2 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-21  6:53 ` [PULL v2 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-21  6:53 ` [PULL v2 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-21  6:53 ` [PULL v2 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-21  6:53 ` [PULL v2 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-21  6:54 ` [PULL v2 09/21] sifive_u: Connect the SiFive PWM device Alistair Francis
2021-09-21  6:54 ` [PULL v2 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-21  6:54 ` [PULL v2 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-21  6:54 ` [PULL v2 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-21  6:54 ` [PULL v2 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-21  6:54 ` Alistair Francis [this message]
2021-09-21  6:54 ` [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Alistair Francis
2021-09-21  6:54 ` [PULL v2 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-21  6:54 ` [PULL v2 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-21  6:54 ` [PULL v2 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions Alistair Francis
2021-09-21  6:54 ` [PULL v2 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-21  6:54 ` [PULL v2 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends Alistair Francis
2021-09-21  6:54 ` [PULL v2 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-21 20:49 ` [PULL v2 00/21] riscv-to-apply queue Richard Henderson

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