From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F85CC433EF for ; Tue, 21 Sep 2021 09:57:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D391D60F4B for ; Tue, 21 Sep 2021 09:57:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D391D60F4B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VaaIbbjuvL0cMWVc6RTfzpxHf45ReLxf2/uMVq4fRo4=; b=GKdN0lLhu1T8H+ Cr8yCPJ9ejJh47waDlf/GQZhQN7o0NHil1LIipEu6n6TaaZaffpO/AwvH+AA45g0iC/LS8+VKePUU yPTR/JQnbT8nebvPyvyhEY3Z07ddQDvFuU6IvYXdcGcTScDvKf8PViaix3PY+QZ5Wq973095IN5uG 1LI15xZXo2lYjpLMWY6AJKSCSt1pO/HiU+hPGHYTDefl+M0A/ThDo91J6t6pQrY/ION8gIHi7yraz RCCd5fHVs7sj5vLmmBYxc+vHRbSxYeyClhWJE58GORXns4pu8Rn891AAbrN97gh0rh1FmSvibI9fY g9lwKkl9E9bne63srphg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mScUV-0045Eo-8J; Tue, 21 Sep 2021 09:55:07 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mScTo-00452u-I7 for linux-arm-kernel@lists.infradead.org; Tue, 21 Sep 2021 09:54:25 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 87B4B61181; Tue, 21 Sep 2021 09:54:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1632218064; bh=6w24sjgU0SgiSE1AUBQG2MopN3G6/i+QeWWBcYAOAIM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UN98KohIcVDtWNpwEr7RNmfdAfgXHyWNtn8rEvMHzyGTr98L878szXbtBb8vAj2tK yADM7nfJCdJNZdJwvpbjM235ISEQ0zEUc52/3OQILd2kTyQc1QrQccP7RQtDjiQqFL x+fFn3fJAHlBOMBJHLn8BUhZtKIBo416d6yC/XDBzkkFCc3tUt1J9c0g77nbWj8CXG AgbVzYdGA5zB3glcO5O40538Q1hDsW8i5PCfNeyL6ZjQfXxqQdKWKQ+YHVTSJFgXLL 5+Ku+i6/yHm85RIQI3qBPuBQxf7uT4yY84ZFoAKa7Lw1kbPIK9oeGa82fQZsJdS1l3 dbKQRKU06Zpiw== From: Ard Biesheuvel To: linux@armlinux.org.uk Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Arnd Bergmann , Kees Cook , Keith Packard , Linus Walleij Subject: [PATCH 04/10] ARM: optimize indirect call to handle_arch_irq for v7 cores Date: Tue, 21 Sep 2021 11:54:02 +0200 Message-Id: <20210921095408.133210-5-ardb@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210921095408.133210-1-ardb@kernel.org> References: <20210921095408.133210-1-ardb@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_025424_657445_BFAF4B4B X-CRM114-Status: GOOD ( 11.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The current irq_handler macro uses a literal load followed by an explicit assignment of lr before an indirect call, both of which are sub-optimal on recent ARM cores. Replace it by a mov_l call, which will evaluate to a movw/movt pair on v7 cores, avoiding one of the two loads, followed by a call to a newly introduced 'bl_m' macro, which will evaluate to a blx instruction on cores that support it. (Setting lr explicitly rather than via a bl or blx instruction confuses the return address prediction that modern out-of-order cores use to speculatively perform the function return.) Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/entry-armv.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index a54b5044d406..21896f702447 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -38,14 +38,12 @@ */ .macro irq_handler #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER - ldr r1, =handle_arch_irq + mov_l r1, handle_arch_irq mov r0, sp - badr lr, 9997f - ldr pc, [r1] + bl_m [r1] #else arch_irq_handler_default #endif -9997: .endm .macro pabt_helper -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel