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[2603:6081:7b01:cbda:24fc:d77e:8558:6741]) by smtp.gmail.com with ESMTPSA id g19sm13176428qki.58.2021.09.21.05.42.22 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Sep 2021 05:42:23 -0700 (PDT) Date: Tue, 21 Sep 2021 08:42:20 -0400 From: Tom Rini To: Mark Kettenis , Bin Meng Cc: kettenis@openbsd.org, u-boot@lists.denx.de, bharat.gooty@broadcom.com, rayagonda.kokatanur@broadcom.com, oliver.graute@kococonnector.com, bin.meng@windriver.com, ycliang@andestech.com, tianrui-wei@outlook.com, stephan@gerhold.net, padmarao.begari@microchip.com, kishon@ti.com, xypron.glpk@gmx.de, michael@walle.cc, masami.hiramatsu@linaro.org, sjg@chromium.org, ashe@kivikakk.ee, wasim.khan@nxp.com, michal.simek@xilinx.com, igor.opaniuk@foundries.io, hs@denx.de, ye.li@nxp.com, sr@denx.de, vabhav.sharma@nxp.com, marek.behun@nic.cz, weijie.gao@mediatek.com, takahiro.akashi@linaro.org, andriy.shevchenko@linux.intel.com, p.yadav@ti.com Subject: Re: [PATCH 1/5] arm: apple: Add initial support for Apple's M1 SoC Message-ID: <20210921124220.GE8579@bill-the-cat> References: <20210918135437.36667-1-kettenis@openbsd.org> <20210918135437.36667-2-kettenis@openbsd.org> <56146c3140e207f5@bloch.sibelius.xs4all.nl> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="xUyMHIOv46mebLva" Content-Disposition: inline In-Reply-To: <56146c3140e207f5@bloch.sibelius.xs4all.nl> X-Clacks-Overhead: GNU Terry Pratchett User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean --xUyMHIOv46mebLva Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Sep 19, 2021 at 10:33:25PM +0200, Mark Kettenis wrote: > > From: Bin Meng > > Date: Sun, 19 Sep 2021 09:17:07 +0800 > >=20 > > Hi Mark, > >=20 > > On Sun, Sep 19, 2021 at 9:04 AM Bin Meng wrote: > > > > > > Hi Mark, > > > > > > On Sat, Sep 18, 2021 at 9:55 PM Mark Kettenis = wrote: > > > > > > > > Add support for Apple's M1 SoC that is used in "Apple Silicon" > > > > Macs. This builds a basic U-Boot that can be used as a payload > > > > for the m1n1 boot loader being developed by the Asahi Linux > > > > project. > > > > > > > > Signed-off-by: Mark Kettenis > > > > --- > > > > arch/arm/Kconfig | 22 ++++ > > > > arch/arm/Makefile | 1 + > > > > arch/arm/mach-apple/Kconfig | 18 ++++ > > > > arch/arm/mach-apple/Makefile | 4 + > > > > arch/arm/mach-apple/board.c | 158 ++++++++++++++++++++++++= ++++ > > > > arch/arm/mach-apple/lowlevel_init.S | 16 +++ > > > > configs/apple_m1_defconfig | 14 +++ > > > > include/configs/apple.h | 38 +++++++ > > > > 8 files changed, 271 insertions(+) > > > > create mode 100644 arch/arm/mach-apple/Kconfig > > > > create mode 100644 arch/arm/mach-apple/Makefile > > > > create mode 100644 arch/arm/mach-apple/board.c > > > > create mode 100644 arch/arm/mach-apple/lowlevel_init.S > > > > create mode 100644 configs/apple_m1_defconfig > > > > create mode 100644 include/configs/apple.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index b5bd3284cd..7cdea1f615 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -895,6 +895,26 @@ config ARCH_NEXELL > > > > select DM > > > > select GPIO_EXTRA_HEADER > > > > > > > > +config ARCH_APPLE > > > > + bool "Apple SoCs" > > > > + select ARM64 > > > > + select LINUX_KERNEL_IMAGE_HEADER > > > > + select POSITION_INDEPENDENT > > > > + select BLK > > > > + select DM > > > > + select DM_KEYBOARD > > > > + select DM_SERIAL > > > > + select DM_USB > > > > + select DM_VIDEO > > > > + select CMD_USB > > > > + select MISC > > > > + select OF_CONTROL > > > > + select OF_BOARD > > > > + select USB > > > > + imply CMD_DM > > > > + imply CMD_GPT > > > > + imply DISTRO_DEFAULTS > > > > + > > > > config ARCH_OWL > > > > bool "Actions Semi OWL SoCs" > > > > select DM > > > > @@ -1932,6 +1952,8 @@ config ISW_ENTRY_ADDR > > > > image headers. > > > > endif > > > > > > > > +source "arch/arm/mach-apple/Kconfig" > > > > + > > > > source "arch/arm/mach-aspeed/Kconfig" > > > > > > > > source "arch/arm/mach-at91/Kconfig" > > > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > > > > index c68e598a67..44178c204b 100644 > > > > --- a/arch/arm/Makefile > > > > +++ b/arch/arm/Makefile > > > > @@ -51,6 +51,7 @@ PLATFORM_CPPFLAGS +=3D $(arch-y) $(tune-y) > > > > > > > > # Machine directory name. This list is sorted alphanumerically > > > > # by CONFIG_* macro name. > > > > +machine-$(CONFIG_ARCH_APPLE) +=3D apple > > > > machine-$(CONFIG_ARCH_ASPEED) +=3D aspeed > > > > machine-$(CONFIG_ARCH_AT91) +=3D at91 > > > > machine-$(CONFIG_ARCH_BCM283X) +=3D bcm283x > > > > diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kcon= fig > > > > new file mode 100644 > > > > index 0000000000..66cab91b2a > > > > --- /dev/null > > > > +++ b/arch/arm/mach-apple/Kconfig > > > > @@ -0,0 +1,18 @@ > > > > +if ARCH_APPLE > > > > + > > > > +config SYS_TEXT_BASE > > > > + default 0x00000000 > > > > + > > > > +config SYS_CONFIG_NAME > > > > + default "apple" > > > > + > > > > +config SYS_SOC > > > > + default "m1" > > > > + > > > > +config SYS_MALLOC_LEN > > > > + default 0x4000000 > > > > + > > > > +config SYS_MALLOC_F_LEN > > > > + default 0x4000 > > > > + > > > > +endif > > > > diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Mak= efile > > > > new file mode 100644 > > > > index 0000000000..e74a8c9df1 > > > > --- /dev/null > > > > +++ b/arch/arm/mach-apple/Makefile > > > > @@ -0,0 +1,4 @@ > > > > +# SPDX-License-Identifier: GPL-2.0+ > > > > + > > > > +obj-y +=3D board.o > > > > +obj-y +=3D lowlevel_init.o > > > > diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/boar= d.c > > > > new file mode 100644 > > > > index 0000000000..0c8b35292e > > > > --- /dev/null > > > > +++ b/arch/arm/mach-apple/board.c > > > > @@ -0,0 +1,158 @@ > > > > +// SPDX-License-Identifier: GPL-2.0+ > > > > +/* > > > > + * (C) Copyright 2021 Mark Kettenis > > > > + */ > > > > + > > > > +#include > > > > +#include > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +DECLARE_GLOBAL_DATA_PTR; > > > > + > > > > +static struct mm_region apple_mem_map[] =3D { > > > > + { > > > > + /* I/O */ > > > > + .virt =3D 0x200000000, > > > > + .phys =3D 0x200000000, > > > > + .size =3D 8UL * SZ_1G, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > > > + PTE_BLOCK_NON_SHARE | > > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > > > + }, { > > > > + /* I/O */ > > > > + .virt =3D 0x500000000, > > > > + .phys =3D 0x500000000, > > > > + .size =3D 2UL * SZ_1G, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > > > + PTE_BLOCK_NON_SHARE | > > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > > > + }, { > > > > + /* I/O */ > > > > + .virt =3D 0x680000000, > > > > + .phys =3D 0x680000000, > > > > + .size =3D SZ_512M, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > > > > + PTE_BLOCK_NON_SHARE | > > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > > > + }, { > > > > + /* PCIE */ > > > > + .virt =3D 0x6a0000000, > > > > + .phys =3D 0x6a0000000, > > > > + .size =3D SZ_512M, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > > > > + PTE_BLOCK_INNER_SHARE | > > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > > > + }, { > > > > + /* PCIE */ > > > > + .virt =3D 0x6c0000000, > > > > + .phys =3D 0x6c0000000, > > > > + .size =3D SZ_1G, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > > > > + PTE_BLOCK_INNER_SHARE | > > > > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > > > > + }, { > > > > + /* RAM */ > > > > + .virt =3D 0x800000000, > > > > + .phys =3D 0x800000000, > > > > + .size =3D 8UL * SZ_1G, > > > > + .attrs =3D PTE_BLOCK_MEMTYPE(MT_NORMAL) | > > > > + PTE_BLOCK_INNER_SHARE > > > > + }, { > > > > + /* Empty entry for framebuffer */ > > > > + 0, > > > > + }, { > > > > + /* List terminator */ > > > > + 0, > > > > + } > > > > +}; > > > > + > > > > +struct mm_region *mem_map =3D apple_mem_map; > > > > + > > > > +int board_init(void) > > > > +{ > > > > + return 0; > > > > +} > > > > + > > > > +int dram_init(void) > > > > +{ > > > > + int index, node, ret; > > > > + fdt_addr_t base; > > > > + fdt_size_t size; > > > > + > > > > + ret =3D fdtdec_setup_mem_size_base(); > > > > + if (ret) > > > > + return ret; > > > > + > > > > + /* Update RAM mapping. */ > > > > > > nits: please remove the ending . > > > > > > > + index =3D ARRAY_SIZE(apple_mem_map) - 3; > >=20 > > This is error prone. Someone else updating apple_mem_map may create an > > incorrect index for us. >=20 > I don't see a better way without introducing more complexity. >=20 > > > > + apple_mem_map[index].virt =3D gd->ram_base; > > > > + apple_mem_map[index].phys =3D gd->ram_base; > > > > + apple_mem_map[index].size =3D gd->ram_size; > > > > + > > > > + node =3D fdt_path_offset(gd->fdt_blob, "/chosen/framebuffer= "); > > > > + if (node < 0) > > > > + return 0; > > > > + > > > > + base =3D fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &s= ize); > > > > + if (base =3D=3D FDT_ADDR_T_NONE) > > > > + return 0; > > > > + > > > > + /* Add framebuffer mapping. */ > > > > > > ditto > > > > > > > + index =3D ARRAY_SIZE(apple_mem_map) - 2; > > > > + apple_mem_map[index].virt =3D base; > > > > + apple_mem_map[index].phys =3D base; > > > > + apple_mem_map[index].size =3D size; > > > > + apple_mem_map[index].attrs =3D PTE_BLOCK_MEMTYPE(MT_NORMAL_= NC) | > > > > + PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_U= XN; > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +int dram_init_banksize(void) > > > > +{ > > > > + return fdtdec_setup_memory_banksize(); > > > > +} > > > > + > > > > +#define APPLE_WDT_BASE 0x23d2b0000ULL > > > > + > > > > +#define APPLE_WDT_SYS_CTL_ENABLE BIT(2) > > > > + > > > > +typedef struct apple_wdt { > > > > + u32 reserved0[3]; > > > > + u32 chip_ctl; > > > > + u32 sys_tmr; > > > > + u32 sys_cmp; > > > > + u32 reserved1; > > > > + u32 sys_ctl; > > > > +} apple_wdt_t; > > > > + > > > > +void reset_cpu(void) > > > > > > This looks like we should add a new sysreset driver for Apple Arm SoC. > > > > > > > +{ > > > > + apple_wdt_t *wdt =3D (apple_wdt_t *)APPLE_WDT_BASE; > > > > + > > > > + writel(0, &wdt->sys_cmp); > > > > + writel(APPLE_WDT_SYS_CTL_ENABLE, &wdt->sys_ctl); > > > > + > > > > + while(1) > > > > + wfi(); > > > > +} > > > > + > > > > +extern long fw_dtb_pointer; > > > > + > > > > +void *board_fdt_blob_setup(void) > > > > +{ > > > > + return (void *)fw_dtb_pointer; > > > > +} > > > > + > > > > +ulong board_get_usable_ram_top(ulong total_size) > > > > +{ > > > > + /* > > > > + * Top part of RAM is used by firmware for things like the > > > > + * framebuffer. This gives us plenty of room to play with. > > > > + */ > > > > + return 0x980000000; > > > > +} > > > > diff --git a/arch/arm/mach-apple/lowlevel_init.S b/arch/arm/mach-ap= ple/lowlevel_init.S > > > > new file mode 100644 > > > > index 0000000000..0f5313163e > > > > --- /dev/null > > > > +++ b/arch/arm/mach-apple/lowlevel_init.S > > > > @@ -0,0 +1,16 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0+ */ > > > > +/* > > > > + * (C) Copyright 2021 Mark Kettenis > > > > + */ > > > > + > > > > +.align 8 > > > > +.global fw_dtb_pointer > > > > +fw_dtb_pointer: > > > > + .quad 0 > > > > > > Is this filled in by m1n1? > >=20 > > Sorry I misread, so this is passed by m1n1 and filled in by U-Boot. I > > think we should stop using CONFIG_OF_BOARD, and for such case we > > should use CONFIG_OF_PRIOR_STAGE. >=20 > Yes, CONFIG_OF_PRIOR_STAGE would work as well. But Tom was talking > about removing that option in favour of CONFIG_OF_BOARD the other day. Yes. I was even looking for some feedback from you, Bin, on converting some boards from CONFIG_OF_PRIOR_STAGE to CONFIG_OF_BOARD. It seems like CONFIG_OF_PRIOR_STAGE is a subset of CONFIG_OF_BOARD, at the cost of possibly a few bytes. --=20 Tom --xUyMHIOv46mebLva Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmFJ0yYACgkQFHw5/5Y0 tyyxnAv/cyCyHhDgj8O5ipq/oQJB6KlrStod45xVDoZX0VdYS/ht+o9uwfWU8ACd Su0pax5/n+STBuP3vPn5IxjUJV40Zoqpl47FO+UJfONAh/xJcQFmRJJcmXOZ7lL2 45Od3KmPIbbM9RYWCs+KHnjw3UnV/4MNrrQdi0Yr58uzENsGbAk0hiPFwCaxGhLP afnGEIqoKCTVyD/6GfTMbkxYMR6/iWKAKRzd23yUevSTEibShpjfKyN+xOByPjA6 uAoii6Zahx2BzvrkPenz/Gd/scFRxnUQYPoVE7OxSqd/mSdir5FMR85RHCJOEU6v lLZz8K7jTclU1uL7+bbcbFwMFE0fcaxh6nvjD4pfXlupMw5QxRv0f+3AK4umNFsn blHbdKV0R0/4k6SymOJVjsyOdnkvFWXYWoWtbd0Iedi1KOZ+Ef0/PteWPBtN8zjA Gf6B0Ye2ViZwt5jJ0alqXyvh9sszYweyVUTNhh9fndOWbMZUXbVGm8Jccppkcuty m9r2e9Q9 =EH0s -----END PGP SIGNATURE----- --xUyMHIOv46mebLva--