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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Subject: [Intel-gfx] [PATCH v2 4/4] drm/i915/fbc: Allow higher compression limits on FBC1
Date: Tue, 21 Sep 2021 18:25:17 +0300	[thread overview]
Message-ID: <20210921152517.803-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210921152517.803-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On FBC1 we can specify an arbitrary cfb stride. The hw will
simply throw away any compressed line that would exceed the
specified limit and keep using the uncompressed data instead.
Thus we can allow arbitrary compression limits.

The one thing we have to keep in mind though is that the cfb
stride is specified in units of 32B (gen2) or 64B (gen3+).
Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide
so as long as we limit outselves to the same 4x compression
limit that FBC2 has we are guaranteed to have a sufficiently
aligned cfb stride.

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1e7d86f04fe9..e8c6c917c5c3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -163,15 +163,13 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 
 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 {
-	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+	struct intel_fbc *fbc = &dev_priv->fbc;
+	const struct intel_fbc_reg_params *params = &fbc->params;
 	int cfb_pitch;
 	int i;
 	u32 fbc_ctl;
 
-	/* Note: fbc.limit == 1 for i8xx */
-	cfb_pitch = params->cfb_size / FBC_LL_SIZE;
-	if (params->fb.stride < cfb_pitch)
-		cfb_pitch = params->fb.stride;
+	cfb_pitch = params->cfb_stride / fbc->limit;
 
 	/* FBC_CTL wants 32B or 64B units */
 	if (DISPLAY_VER(dev_priv) == 2)
@@ -517,18 +515,14 @@ static int intel_fbc_min_limit(int fb_cpp)
 
 static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
 {
-	/*
-	 * FIXME: FBC1 can have arbitrary cfb stride,
-	 * so we could support different compression ratios.
-	 */
-	if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
-		return 1;
-
 	/* WaFbcOnly1to1Ratio:ctg */
 	if (IS_G4X(dev_priv))
 		return 1;
 
-	/* FBC2 can only do 1:1, 1:2, 1:4 */
+	/*
+	 * FBC2 can only do 1:1, 1:2, 1:4, we limit
+	 * FBC1 to the same out of convenience.
+	 */
 	return 4;
 }
 
-- 
2.32.0


  parent reply	other threads:[~2021-09-21 15:25 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 15:25 [Intel-gfx] [PATCH v2 0/4] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Rework cfb " Ville Syrjala
2021-09-22 18:26   ` Shankar, Uma
2021-09-23  4:21   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
2021-09-21 15:25 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
2021-09-21 18:12   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-21 15:25 ` Ville Syrjala [this message]
2021-09-21 17:27 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/fbc: Rework CFB stride/size calculations (rev3) Patchwork
2021-09-21 21:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev4) Patchwork
2021-09-21 21:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-21 22:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev5) Patchwork
2021-09-21 22:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-22  0:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-22 19:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev6) Patchwork
2021-09-22 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-22 21:23 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-23  4:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev7) Patchwork
2021-09-23  5:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-23  7:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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