From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDEEC433EF for ; Tue, 21 Sep 2021 15:52:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A78761183 for ; Tue, 21 Sep 2021 15:52:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3A78761183 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C87A6EA53; Tue, 21 Sep 2021 15:52:35 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6EC386EA4A for ; Tue, 21 Sep 2021 15:52:33 +0000 (UTC) X-UUID: 98464a54bfaf4c84bd4c589ad8829dbe-20210921 X-UUID: 98464a54bfaf4c84bd4c589ad8829dbe-20210921 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 46428423; Tue, 21 Sep 2021 23:52:28 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 23:52:28 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 23:52:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Sep 2021 23:52:28 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" CC: Enric Balletbo i Serra , Maxime Coquelin , David Airlie , Daniel Vetter , Alexandre Torgue , , , , , , Fabien Parent , Yongqiang Niu , , , , , , , , Subject: [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195 Date: Tue, 21 Sep 2021 23:52:07 +0800 Message-ID: <20210921155218.10387-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210921155218.10387-1-jason-jh.lin@mediatek.com> References: <20210921155218.10387-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" add MERGE additional properties description for mt8195: 1. async clock 2. fifo setting enable 3. reset controller Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,merge.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 75beeb207ceb..542dd7137d3b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,6 +38,19 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display + function blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency + buffer to ensure that the back-end panel display data will not be + underrun, a little more data is needed in the fifo. + According to the merge fifo settings, when the water level is detected + to be insufficient, it will trigger RDMA sending ultra and preulra + command to SMI to speed up the data rate. + type: boolean mediatek,gce-client-reg: description: @@ -50,6 +63,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. + maxItems: 1 + required: - compatible - reg @@ -67,3 +85,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E34B7C433EF for ; Tue, 21 Sep 2021 15:59:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B492760E94 for ; Tue, 21 Sep 2021 15:59:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B492760E94 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1SRMAOWsUUxVSXtJ63H+sdfeAwm/Tn3/ajnq4nu49gU=; b=e5MrMOSzpTdseA UphuAwqaNLNEq8dZuxv1AbcOTTrC94A9SsJJJewIeIV6TDJ3+uREbT4XUPzCLEZkFHMSPcOy+9UvO BFCSArzpCHhlQimHuDj8VtPhoIJU/wKhGbt6eql+o/Y09EriEYUwbXL76wHN5F429f3Y/sgG7UrsU tZ8aTDdAy3TCAN6cmismm/WzClkB8A5OILV8ubpgjoq4NVFjLY0aIoMaLILVOWIqX0yTITN73apL6 giba74/wcxSTthw8wkme/0T379uhbfkbrVJdz13TjmdaALQuVaHgkqYbEUBmIaInh1kw6MqIPxTBh hXs4CwulhrrU2DxpaRXw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSiBJ-0052CM-E7; Tue, 21 Sep 2021 15:59:41 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSi4k-004yPi-5p; Tue, 21 Sep 2021 15:52:57 +0000 X-UUID: a7cb528622bd4ad3b4ca82a3dab2ff0e-20210921 X-UUID: a7cb528622bd4ad3b4ca82a3dab2ff0e-20210921 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1124988421; Tue, 21 Sep 2021 08:52:36 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 08:52:35 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 23:52:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Sep 2021 23:52:28 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" CC: Enric Balletbo i Serra , Maxime Coquelin , David Airlie , Daniel Vetter , Alexandre Torgue , , , , , , Fabien Parent , Yongqiang Niu , , , , , , , , Subject: [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195 Date: Tue, 21 Sep 2021 23:52:07 +0800 Message-ID: <20210921155218.10387-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210921155218.10387-1-jason-jh.lin@mediatek.com> References: <20210921155218.10387-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_085254_280948_940B9C93 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org add MERGE additional properties description for mt8195: 1. async clock 2. fifo setting enable 3. reset controller Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,merge.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 75beeb207ceb..542dd7137d3b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,6 +38,19 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display + function blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency + buffer to ensure that the back-end panel display data will not be + underrun, a little more data is needed in the fifo. + According to the merge fifo settings, when the water level is detected + to be insufficient, it will trigger RDMA sending ultra and preulra + command to SMI to speed up the data rate. + type: boolean mediatek,gce-client-reg: description: @@ -50,6 +63,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. + maxItems: 1 + required: - compatible - reg @@ -67,3 +85,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5097C433F5 for ; Tue, 21 Sep 2021 16:01:59 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7D0060F6E for ; Tue, 21 Sep 2021 16:01:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A7D0060F6E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E4yhBDZCsvcfssSDPUyUUQCph3tFgQXBNF5MvkfqiQk=; b=Pr3evnoNhhuja9 9cvvFw8ilII9JjXepvHBBf9TicnIiJJcCTud81S/UecKSKpjVRdo/f20LukDpC3v7kE2ioGX81dyU dqkHlhmsZ54SNHlSFmvZeZ6JeEmKu3v6A4kfmaHUCO8bk8kCw04hhzGcgc3jNC0Pt6PXj1S0ovogn AdJQlOldZN6UHDsXefA9Jx6O7vEuvughmDiRMJrW1zIjfSEstabAurQBA95e0kR2lSwToZ0VRNCzr FfNXy5IVikR+xqgw+ToMTMx6bNcy1fGfgnUE/r850O1F4zFpJyj3/LaAtv17+5ukEUGWJ0E0FVhKd k9F+FOnmgUxPKolQ7rnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSiBR-0052Dl-MV; Tue, 21 Sep 2021 15:59:50 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSi4k-004yPi-5p; Tue, 21 Sep 2021 15:52:57 +0000 X-UUID: a7cb528622bd4ad3b4ca82a3dab2ff0e-20210921 X-UUID: a7cb528622bd4ad3b4ca82a3dab2ff0e-20210921 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1124988421; Tue, 21 Sep 2021 08:52:36 -0700 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 08:52:35 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 21 Sep 2021 23:52:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 21 Sep 2021 23:52:28 +0800 From: jason-jh.lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" CC: Enric Balletbo i Serra , Maxime Coquelin , David Airlie , Daniel Vetter , Alexandre Torgue , , , , , , Fabien Parent , Yongqiang Niu , , , , , , , , Subject: [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195 Date: Tue, 21 Sep 2021 23:52:07 +0800 Message-ID: <20210921155218.10387-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210921155218.10387-1-jason-jh.lin@mediatek.com> References: <20210921155218.10387-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210921_085254_280948_940B9C93 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org add MERGE additional properties description for mt8195: 1. async clock 2. fifo setting enable 3. reset controller Signed-off-by: jason-jh.lin --- .../display/mediatek/mediatek,merge.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index 75beeb207ceb..542dd7137d3b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -38,6 +38,19 @@ properties: clocks: items: - description: MERGE Clock + - description: MERGE Async Clock + Controlling the synchronous process between MERGE and other display + function blocks cross clock domain. + + mediatek,merge-fifo-en: + description: + The setting of merge fifo is mainly provided for the display latency + buffer to ensure that the back-end panel display data will not be + underrun, a little more data is needed in the fifo. + According to the merge fifo settings, when the water level is detected + to be insufficient, it will trigger RDMA sending ultra and preulra + command to SMI to speed up the data rate. + type: boolean mediatek,gce-client-reg: description: @@ -50,6 +63,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array maxItems: 1 + resets: + description: reset controller + See Documentation/devicetree/bindings/reset/reset.txt for details. + maxItems: 1 + required: - compatible - reg @@ -67,3 +85,16 @@ examples: power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel