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From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: WANG Xuerui <git@xen0n.name>
Subject: [PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops
Date: Wed, 22 Sep 2021 04:18:57 +0800	[thread overview]
Message-ID: <20210921201915.601245-13-git@xen0n.name> (raw)
In-Reply-To: <20210921201915.601245-1-git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 tcg/loongarch64/tcg-target-con-set.h |   2 +
 tcg/loongarch64/tcg-target.c.inc     | 101 +++++++++++++++++++++++++++
 2 files changed, 103 insertions(+)

diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 7e459490ea..9ac24b8ad0 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -16,3 +16,5 @@
  */
 C_O0_I1(r)
 C_O1_I1(r, r)
+C_O1_I2(r, r, rC)
+C_O1_I2(r, r, rU)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index e000a31a06..89fdb6d7c3 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -374,6 +374,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 {
     TCGArg a0 = args[0];
     TCGArg a1 = args[1];
+    TCGArg a2 = args[2];
+    int c2 = const_args[2];
 
     switch (opc) {
     case INDEX_op_mb:
@@ -419,6 +421,79 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_opc_srai_d(s, a0, a1, 32);
         break;
 
+    case INDEX_op_not_i32:
+    case INDEX_op_not_i64:
+        tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
+        break;
+
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+        if (c2) {
+            tcg_out_opc_ori(s, a0, a1, a2);
+            tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
+        } else {
+            tcg_out_opc_nor(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+        if (c2) {
+            /* guaranteed to fit due to constraint */
+            tcg_out_opc_andi(s, a0, a1, ~a2);
+        } else {
+            tcg_out_opc_andn(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        if (c2) {
+            /* guaranteed to fit due to constraint */
+            tcg_out_opc_ori(s, a0, a1, ~a2);
+        } else {
+            tcg_out_opc_orn(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+        if (c2) {
+            /* guaranteed to fit due to constraint */
+            tcg_out_opc_xori(s, a0, a1, ~a2);
+        } else {
+            tcg_out_opc_nor(s, a0, a2, TCG_REG_ZERO);
+            tcg_out_opc_xor(s, a0, a1, a0);
+        }
+        break;
+
+    case INDEX_op_and_i32:
+    case INDEX_op_and_i64:
+        if (c2) {
+            tcg_out_opc_andi(s, a0, a1, a2);
+        } else {
+            tcg_out_opc_and(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_or_i32:
+    case INDEX_op_or_i64:
+        if (c2) {
+            tcg_out_opc_ori(s, a0, a1, a2);
+        } else {
+            tcg_out_opc_or(s, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_xor_i32:
+    case INDEX_op_xor_i64:
+        if (c2) {
+            tcg_out_opc_xori(s, a0, a1, a2);
+        } else {
+            tcg_out_opc_xor(s, a0, a1, a2);
+        }
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     default:
@@ -446,8 +521,34 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extrl_i64_i32:
     case INDEX_op_extrh_i64_i32:
     case INDEX_op_ext_i32_i64:
+    case INDEX_op_not_i32:
+    case INDEX_op_not_i64:
         return C_O1_I1(r, r);
 
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        /*
+         * LoongArch insns for these ops don't have reg-imm forms, but we
+         * can express using andi/ori/xori if ~constant satisfies
+         * TCG_CT_CONST_U12.
+         */
+        return C_O1_I2(r, r, rC);
+
+    case INDEX_op_and_i32:
+    case INDEX_op_and_i64:
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+    case INDEX_op_or_i32:
+    case INDEX_op_or_i64:
+    case INDEX_op_xor_i32:
+    case INDEX_op_xor_i64:
+        /* LoongArch reg-imm bitops have their imms ZERO-extended */
+        return C_O1_I2(r, r, rU);
+
     default:
         g_assert_not_reached();
     }
-- 
2.33.0



  parent reply	other threads:[~2021-09-21 20:29 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 20:18 [PATCH v2 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-22  3:55   ` Richard Henderson
2021-09-22  4:33     ` WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-22  3:59   ` Richard Henderson
2021-09-21 20:18 ` [PATCH v2 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-22  4:02   ` Richard Henderson
2021-09-21 20:18 ` [PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-22  4:03   ` Richard Henderson
2021-09-21 20:18 ` [PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-22  4:25   ` Richard Henderson
2021-09-22 15:16     ` WANG Xuerui
2021-09-22 15:17       ` Richard Henderson
2021-09-22 17:22         ` WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-21 20:18 ` WANG Xuerui [this message]
2021-09-22  4:35   ` [PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops Richard Henderson
2021-09-22 17:23     ` WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-21 20:18 ` [PATCH v2 14/30] tcg/loongarch64: Implement bswap32_i32/bswap32_i64/bswap64_i64 WANG Xuerui
2021-09-22 14:54   ` Richard Henderson
2021-09-22 17:24     ` WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-22 14:57   ` Richard Henderson
2021-09-21 20:19 ` [PATCH v2 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-22 14:59   ` Richard Henderson
2021-09-21 20:19 ` [PATCH v2 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-22 15:01   ` Richard Henderson
2021-09-21 20:19 ` [PATCH v2 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-22 15:13   ` Richard Henderson
2021-09-22 17:26     ` WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-22 15:16   ` Richard Henderson
2021-09-21 20:19 ` [PATCH v2 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-22 16:29   ` Richard Henderson
2021-09-22 17:32     ` WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-22 16:39   ` Richard Henderson
2021-09-21 20:19 ` [PATCH v2 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-22 16:51   ` Richard Henderson
2021-09-22 17:35     ` WANG Xuerui
2021-09-21 20:19 ` [PATCH v2 30/30] configure, meson.build: Mark support " WANG Xuerui
2021-09-22 16:53   ` Richard Henderson

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