From: Leo Yu-Chi Liang <ycliang@andestech.com>
To: <u-boot@lists.denx.de>
Cc: <rick@andestech.com>, Leo Yu-Chi Liang <ycliang@andestech.com>
Subject: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350
Date: Thu, 23 Sep 2021 10:34:29 +0800 [thread overview]
Message-ID: <20210923023429.18389-1-ycliang@andestech.com> (raw)
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/cpu/ax25/cpu.c | 42 +++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index f092600e14..c4c2de2ef0 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -9,6 +9,22 @@
#include <cpu_func.h>
#include <irq_func.h>
#include <asm/cache.h>
+#include <asm/csr.h>
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
+
+#define V5_MCACHE_CTL_IC_EN_OFFSET 0
+#define V5_MCACHE_CTL_DC_EN_OFFSET 1
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
+#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+
/*
* cleanup_before_linux() is called just before we call linux
@@ -27,3 +43,29 @@ int cleanup_before_linux(void)
return 0;
}
+
+void harts_early_init(void)
+{
+ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+ unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+ csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
+
+ /*
+ * Check DC_COHEN_EN, if cannot write to mcache_ctl,
+ * we assume this bitmap not support L2 CM
+ */
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
+ /* Wait for DC_COHSTA bit be set */
+ while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ }
+ }
+}
--
2.17.0
next reply other threads:[~2021-09-23 2:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 2:34 Leo Yu-Chi Liang [this message]
[not found] ` <PU1PR03MB299758CB10061BE4DB3F600FC1A49@PU1PR03MB2997.apcprd03.prod.outlook.com>
2021-09-24 0:32 ` [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350 Rick Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210923023429.18389-1-ycliang@andestech.com \
--to=ycliang@andestech.com \
--cc=rick@andestech.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.