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* [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
@ 2021-09-23  8:48 Stanislav Lisovskiy
  2021-09-23  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 18+ messages in thread
From: Stanislav Lisovskiy @ 2021-09-23  8:48 UTC (permalink / raw)
  To: intel-gfx
  Cc: Stanislav.Lisovskiy, jani.saarinen, maarten.lankhorst, matthew.d.roper

TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  3 ++
 drivers/gpu/drm/i915/display/intel_fb.c       | 12 +++++-
 drivers/gpu/drm/i915/display/intel_fbc.c      |  1 +
 .../drm/i915/display/skl_universal_plane.c    | 37 ++++++++++++++-----
 drivers/gpu/drm/i915/gem/i915_gem_object.h    |  8 +++-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c    |  4 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/i915_pci.c               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 drivers/gpu/drm/i915/intel_pm.c               |  1 +
 include/uapi/drm/drm_fourcc.h                 |  8 ++++
 include/uapi/drm/i915_drm.h                   |  3 +-
 15 files changed, 71 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 23b1e0ccc72d..7564b8812c5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1335,6 +1335,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_F:
 		obj->tiling_and_stride =
 			plane_config->fb->base.pitches[0] |
 			plane_config->tiling;
@@ -1376,6 +1377,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 		break;
 	default:
 		drm_dbg(&dev_priv->drm,
@@ -9282,6 +9284,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
 		case I915_FORMAT_MOD_X_TILED:
 		case I915_FORMAT_MOD_Y_TILED:
 		case I915_FORMAT_MOD_Yf_TILED:
+		case I915_FORMAT_MOD_F_TILED:
 			break;
 		default:
 			drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index e4b8602ec0cd..d88070406098 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -101,6 +101,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		else
 			return 512;
+	case I915_FORMAT_MOD_F_TILED:
+		/*
+		 * Each 4K tile consists of 64B(8*8) subtiles, with
+		 * same shape as Y Tile(i.e 4*16B OWords)
+		 */
+		return 128;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		if (is_ccs_plane(fb, color_plane))
 			return 128;
@@ -185,6 +191,8 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	switch (fb_modifier) {
 	case I915_FORMAT_MOD_X_TILED:
 		return I915_TILING_X;
+	case I915_FORMAT_MOD_F_TILED:
+		return I915_TILING_F;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
@@ -264,6 +272,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
 		return 1 * 1024 * 1024;
 	default:
@@ -1282,7 +1291,8 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	} else {
 		if (tiling == I915_TILING_X) {
 			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
-		} else if (tiling == I915_TILING_Y) {
+		} else if ((tiling == I915_TILING_Y) ||
+			   (tiling == I915_TILING_F)) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "No Y tiling for legacy addfb\n");
 			goto err;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b1c1a23c36be..015005cf2ba1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -679,6 +679,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 	switch (modifier) {
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 		return DISPLAY_VER(dev_priv) >= 9;
 	case I915_FORMAT_MOD_X_TILED:
 		return true;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b6..09c00fc099f2 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -206,6 +206,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
+static const u64 dg2_plane_format_modifiers[] = {
+	I915_FORMAT_MOD_X_TILED,
+	I915_FORMAT_MOD_F_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
 	switch (format) {
@@ -793,6 +800,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_X;
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
+	case I915_FORMAT_MOD_F_TILED:
+		return PLANE_CTL_TILED_F;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1240,6 +1249,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_F_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
@@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			return false;
 		break;
+	case I915_FORMAT_MOD_F_TILED:
+		if (!HAS_FTILE(dev_priv))
+			return false;
+		fallthrough;
 	default:
 		return false;
 	}
@@ -1981,9 +1995,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_Y216:
 	case DRM_FORMAT_XVYU12_16161616:
 	case DRM_FORMAT_XVYU16161616:
-		if (modifier == DRM_FORMAT_MOD_LINEAR ||
-		    modifier == I915_FORMAT_MOD_X_TILED ||
-		    modifier == I915_FORMAT_MOD_Y_TILED)
+		if (!is_ccs_modifier(modifier))
 			return true;
 		fallthrough;
 	default:
@@ -1994,8 +2006,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
 					    enum plane_id plane_id)
 {
+	if (HAS_FTILE(dev_priv))
+		return dg2_plane_format_modifiers;
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return adlp_step_a_plane_format_modifiers;
 	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
 		return gen12_plane_format_modifiers_mc_ccs;
@@ -2265,11 +2279,16 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
-	case PLANE_CTL_TILED_YF:
-		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
-		else
-			fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
+		if (DISPLAY_VER(dev_priv) >= 13) {
+			plane_config->tiling = I915_TILING_F;
+			fb->modifier = I915_FORMAT_MOD_F_TILED;
+		} else {
+			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+			else
+				fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+		}
 		break;
 	default:
 		MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3043fcbd31bd..d96bcab1f3e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -326,7 +326,13 @@ static inline unsigned int
 i915_gem_tile_height(unsigned int tiling)
 {
 	GEM_BUG_ON(!tiling);
-	return tiling == I915_TILING_Y ? 32 : 8;
+	switch (tiling) {
+	case I915_TILING_Y:
+	case I915_TILING_F:
+		return 32;
+	default:
+		return 8;
+	}
 }
 
 static inline unsigned int
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..520b8fb7c870 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -145,7 +145,8 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
 	}
 
 	if (GRAPHICS_VER(i915) == 2 ||
-	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
+	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)) ||
+	     tiling == I915_TILING_F)
 		tile_width = 128;
 	else
 		tile_width = 512;
@@ -438,6 +439,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_F:
 		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
 		break;
 	default:
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..f748bcbf46c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -77,7 +77,8 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
 		val <<= 32;
 		val |= fence->start;
 		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
-		if (fence->tiling == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y ||
+		    fence->tiling == I915_TILING_F)
 			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 		val |= I965_FENCE_REG_VALID;
 	}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..f43968fc16fe 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -82,6 +82,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
 	case I915_TILING_NONE: return ' ';
 	case I915_TILING_X: return 'X';
 	case I915_TILING_Y: return 'Y';
+	case I915_TILING_F: return 'F';
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc355aa05dbf..dafa8b1f365a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1586,6 +1586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 
 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
+#define HAS_FTILE(dev_priv)    (INTEL_INFO(dev_priv)->has_ftile)
 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4a6a9dcf182..81963d5876ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -970,6 +970,7 @@ static const struct intel_device_info adl_p_info = {
 	.display.has_cdclk_crawl = 1,
 	.display.has_modular_fia = 1,
 	.display.has_psr_hw_tracking = 0,
+	.has_ftile = 1, \
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cad84c3b864b..55c8a47ba047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,6 +7192,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_TILED_F			(5 << 10)
 #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..76f783c10f81 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
 	func(has_64bit_reloc); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
+	func(has_ftile); \
 	func(has_global_mocs); \
 	func(has_gt_uc); \
 	func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 74fd6aa7afc7..6e68f259c4c1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5362,6 +5362,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 	}
 
 	wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+		      modifier == I915_FORMAT_MOD_F_TILED ||
 		      modifier == I915_FORMAT_MOD_Yf_TILED ||
 		      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 		      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 45a914850be0..a7d3027b5bdc 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -558,6 +558,14 @@ extern "C" {
  * pitch is required to be a multiple of 4 tile widths.
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_F_TILED         fourcc_mod_code(INTEL, 10)
 
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..d7dc421c6134 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE	0
 #define I915_TILING_X		1
 #define I915_TILING_Y		2
-#define I915_TILING_LAST	I915_TILING_Y
+#define I915_TILING_F		3
+#define I915_TILING_LAST	I915_TILING_F
 
 #define I915_BIT_6_SWIZZLE_NONE		0
 #define I915_BIT_6_SWIZZLE_9		1
-- 
2.24.1.485.gad05a3d8e5


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Tile F plane format support
  2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
@ 2021-09-23  9:20 ` Patchwork
  2021-09-23  9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-09-23  9:20 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Tile F plane format support
URL   : https://patchwork.freedesktop.org/series/94983/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a9ee2ce07783 drm/i915: Tile F plane format support
-:281: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#281: FILE: drivers/gpu/drm/i915/i915_pci.c:973:
+	.has_ftile = 1, \

total: 0 errors, 1 warnings, 0 checks, 248 lines checked



^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Tile F plane format support
  2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
  2021-09-23  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2021-09-23  9:49 ` Patchwork
  2021-09-23 10:28 ` [Intel-gfx] [PATCH] " Jani Nikula
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-09-23  9:49 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 4985 bytes --]

== Series Details ==

Series: drm/i915: Tile F plane format support
URL   : https://patchwork.freedesktop.org/series/94983/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10630 -> Patchwork_21143
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/index.html

Known issues
------------

  Here are the changes found in Patchwork_21143 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [PASS][2] -> [FAIL][3] ([i915#1888]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html

  * igt@i915_module_load@reload:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-WARN][6] ([i915#1982])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-8809g/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
    - fi-kbl-8809g:       NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-8809g/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-rkl-guc:         [PASS][12] -> [SKIP][13] ([i915#3919])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/fi-rkl-guc/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-rkl-guc/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  * igt@kms_psr@cursor_plane_move:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][14] ([fdo#109271]) +37 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3919]: https://gitlab.freedesktop.org/drm/intel/issues/3919
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (33 -> 29)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (5): bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10630 -> Patchwork_21143

  CI-20190529: 20190529
  CI_DRM_10630: a3ffd2c50784aebf118e55aee39f223a44150eca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21143: a9ee2ce07783cb017eb23becece43bc81b146206 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a9ee2ce07783 drm/i915: Tile F plane format support

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/index.html

[-- Attachment #2: Type: text/html, Size: 6528 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
  2021-09-23  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
  2021-09-23  9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-23 10:28 ` Jani Nikula
  2021-09-23 10:44   ` Lisovskiy, Stanislav
  2021-09-23 11:03 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
  2021-09-23 15:49 ` [Intel-gfx] [PATCH] " Ville Syrjälä
  4 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2021-09-23 10:28 UTC (permalink / raw)
  To: Stanislav Lisovskiy, intel-gfx
  Cc: Stanislav.Lisovskiy, jani.saarinen, maarten.lankhorst, matthew.d.roper

On Thu, 23 Sep 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> @@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			return false;
>  		break;
> +	case I915_FORMAT_MOD_F_TILED:
> +		if (!HAS_FTILE(dev_priv))
> +			return false;
> +		fallthrough;
>  	default:
>  		return false;
>  	}

Seems odd.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23 10:28 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2021-09-23 10:44   ` Lisovskiy, Stanislav
  2021-09-23 11:51     ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-23 10:44 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx, jani.saarinen, maarten.lankhorst, matthew.d.roper

On Thu, Sep 23, 2021 at 01:28:21PM +0300, Jani Nikula wrote:
> On Thu, 23 Sep 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> > @@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >  			return false;
> >  		break;
> > +	case I915_FORMAT_MOD_F_TILED:
> > +		if (!HAS_FTILE(dev_priv))
> > +			return false;
> > +		fallthrough;
> >  	default:
> >  		return false;
> >  	}
> 
> Seems odd.

I agree, however this wasn't even added by me.
This patch got changed in ridiculous ways since last time,
I ever touched it. 
Currently we have it internally exactly same way(wondering why)
Unfortunately didn't pay attention to this, was assuming
that if its r-bed and pushed - can trust it.

Stan


> 
> BR,
> Jani.
> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Tile F plane format support
  2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
                   ` (2 preceding siblings ...)
  2021-09-23 10:28 ` [Intel-gfx] [PATCH] " Jani Nikula
@ 2021-09-23 11:03 ` Patchwork
  2021-09-23 15:49 ` [Intel-gfx] [PATCH] " Ville Syrjälä
  4 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2021-09-23 11:03 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 30260 bytes --]

== Series Details ==

Series: drm/i915: Tile F plane format support
URL   : https://patchwork.freedesktop.org/series/94983/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10630_full -> Patchwork_21143_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_21143_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_mm@all@insert:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([i915#2485])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl10/igt@drm_mm@all@insert.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl2/igt@drm_mm@all@insert.html

  * igt@gem_create@create-massive:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-snb7/igt@gem_ctx_persistence@process.html

  * igt@gem_eio@in-flight-suspend:
    - shard-apl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-apl3/igt@gem_eio@in-flight-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_flush@basic-wb-set-default:
    - shard-glk:          [PASS][10] -> [INCOMPLETE][11] ([i915#2944])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk8/igt@gem_exec_flush@basic-wb-set-default.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk3/igt@gem_exec_flush@basic-wb-set-default.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][12] ([i915#768])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][13] ([i915#3002])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl6/igt@gem_userptr_blits@input-checking.html

  * igt@gem_workarounds@suspend-resume:
    - shard-snb:          [PASS][14] -> [TIMEOUT][15] ([i915#2808])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-snb7/igt@gem_workarounds@suspend-resume.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-snb7/igt@gem_workarounds@suspend-resume.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-iclb:         NOTRUN -> [SKIP][16] ([i915#2856])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][17] -> [DMESG-WARN][18] ([i915#1436] / [i915#716])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl6/igt@gen9_exec_parse@allowed-single.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl10/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#2856]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-snb:          NOTRUN -> [SKIP][20] ([fdo#109271]) +288 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-snb5/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-iclb:         NOTRUN -> [SKIP][21] ([i915#1769])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([fdo#110725] / [fdo#111614])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3777]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +3 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][25] ([i915#3689] / [i915#3886])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([fdo#109278] / [i915#3886])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][27] ([fdo#109278])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-apl:          NOTRUN -> [SKIP][29] ([fdo#109271]) +175 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl7/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_chamelium@hdmi-crc-multiple:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_chamelium@hdmi-crc-multiple.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@vga-edid-read:
    - shard-skl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_chamelium@vga-edid-read.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-snb:          NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-b-gamma:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#109284] / [fdo#111827])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_color_chamelium@pipe-b-gamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271]) +7 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#4103])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#2346])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][39] -> [FAIL][40] ([i915#2346] / [i915#533])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([i915#79])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][43] -> [DMESG-WARN][44] ([i915#180]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][45] ([i915#180])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][46] -> [FAIL][47] ([i915#2122])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
    - shard-iclb:         [PASS][48] -> [SKIP][49] ([i915#3701])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271]) +36 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109280]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#111825]) +3 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][53] -> [FAIL][54] ([i915#1188])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@static-toggle:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#1187])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_hdr@static-toggle.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-tglb:         [PASS][57] -> [INCOMPLETE][58] ([i915#4182])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][60] ([i915#265])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2733])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
    - shard-skl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [PASS][64] -> [SKIP][65] ([fdo#109642] / [fdo#111068] / [i915#658])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb7/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_basic:
    - shard-tglb:         NOTRUN -> [FAIL][66] ([i915#132] / [i915#3467])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_psr@psr2_basic.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][67] -> [SKIP][68] ([fdo#109441]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
    - shard-tglb:         [PASS][69] -> [INCOMPLETE][70] ([i915#456]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb7/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2437]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl7/igt@kms_writeback@writeback-check-output.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][72] -> [FAIL][73] ([i915#1542])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl5/igt@perf@polling-parameterized.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl7/igt@perf@polling-parameterized.html

  * igt@perf@polling-small-buf:
    - shard-skl:          [PASS][74] -> [FAIL][75] ([i915#1722])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl7/igt@perf@polling-small-buf.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl2/igt@perf@polling-small-buf.html

  * igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([fdo#109291])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl1/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@sema-10:
    - shard-skl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@sysfs_clients@sema-10.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [SKIP][79] ([i915#658]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb4/igt@feature_discovery@psr2.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb2/igt@feature_discovery@psr2.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [TIMEOUT][81] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb4/igt@gem_eio@unwedge-stress.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [FAIL][83] ([i915#2846]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk7/igt@gem_exec_fair@basic-deadline.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk1/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][85] ([i915#2842]) -> [PASS][86] +4 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][87] ([i915#2190]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_workarounds@suspend-resume:
    - shard-kbl:          [DMESG-WARN][89] ([i915#180]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-kbl1/igt@gem_workarounds@suspend-resume.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-kbl4/igt@gem_workarounds@suspend-resume.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][91] ([i915#180]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl2/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][93] ([i915#454]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb5/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_color@pipe-c-ctm-0-25:
    - shard-skl:          [DMESG-WARN][95] ([i915#1982]) -> [PASS][96] +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl1/igt@kms_color@pipe-c-ctm-0-25.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][97] ([i915#2828] / [i915#456]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
    - shard-kbl:          [FAIL][99] ([i915#79]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
    - shard-iclb:         [SKIP][101] ([i915#3701]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [INCOMPLETE][103] ([i915#2411] / [i915#456]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][105] ([i915#1188]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl5/igt@kms_hdr@bpc-switch.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl7/igt@kms_hdr@bpc-switch.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-skl:          [INCOMPLETE][107] ([i915#198]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][109] ([fdo#108145] / [i915#265]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [FAIL][111] ([i915#3343]) -> [SKIP][112] ([i915#3288])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][113] ([i915#2684]) -> [WARN][114] ([i915#1804] / [i915#2684])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][115] ([i915#658]) -> [SKIP][116] ([i915#2920]) +3 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][117], [FAIL][118]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122]) ([i915#1610] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-apl7/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-apl1/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl6/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl8/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-apl6/igt@runner@aborted.html
    - shard-glk:          ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#3363] / [k.org#202321]) -> ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#1814] / [i915#2426] / [i915#2722] / [i915#3002] / [i915#3363] / [k.org#202321])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk2/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk2/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk3/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-glk9/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk7/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk3/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk5/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk9/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-glk5/igt@runner@aborted.html
    - shard-skl:          ([FAIL][132], [FAIL][133]) ([i915#3002] / [i915#3363]) -> ([FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#3002] / [i915#3363])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl9/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10630/shard-skl9/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl3/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl4/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/shard-skl10/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1187]: https://gitlab.freedesktop.org/drm/intel/issues/1187
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
  [i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21143/index.html

[-- Attachment #2: Type: text/html, Size: 35944 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23 10:44   ` Lisovskiy, Stanislav
@ 2021-09-23 11:51     ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-23 11:51 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx, jani.saarinen, maarten.lankhorst, matthew.d.roper

On Thu, Sep 23, 2021 at 01:44:11PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Sep 23, 2021 at 01:28:21PM +0300, Jani Nikula wrote:
> > On Thu, 23 Sep 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> > > @@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > >  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >  			return false;
> > >  		break;
> > > +	case I915_FORMAT_MOD_F_TILED:
> > > +		if (!HAS_FTILE(dev_priv))
> > > +			return false;
> > > +		fallthrough;
> > >  	default:
> > >  		return false;
> > >  	}
> > 
> > Seems odd.
> 
> I agree, however this wasn't even added by me.
> This patch got changed in ridiculous ways since last time,
> I ever touched it. 
> Currently we have it internally exactly same way(wondering why)
> Unfortunately didn't pay attention to this, was assuming
> that if its r-bed and pushed - can trust it.

Actually checked - seems to be result of wrong merge conflict resolution
by me.

It was initially that way:

-	case DRM_FORMAT_MOD_LINEAR:
-	case I915_FORMAT_MOD_X_TILED:
-		break;
 	case I915_FORMAT_MOD_Y_TILED:
 		if (IS_DG2(dev_priv))
 			return false;
@@ -1928,6 +1934,13 @@  static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (IS_DG2(dev_priv))
 			return false;
 		break;
+	case I915_FORMAT_MOD_F_TILED:
+		if (!HAS_FTILE(dev_priv))
+			return false;
+		fallthrough;
+	case DRM_FORMAT_MOD_LINEAR:
+	case I915_FORMAT_MOD_X_TILED:
+		break;

So my bad here. Need to put this back.

Stan


> 
> Stan
> 
> 
> > 
> > BR,
> > Jani.
> > 
> > 
> > -- 
> > Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
                   ` (3 preceding siblings ...)
  2021-09-23 11:03 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
@ 2021-09-23 15:49 ` Ville Syrjälä
  2021-09-23 16:19   ` Lisovskiy, Stanislav
  2021-09-27 18:23   ` Matt Roper
  4 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjälä @ 2021-09-23 15:49 UTC (permalink / raw)
  To: Stanislav Lisovskiy
  Cc: intel-gfx, jani.saarinen, maarten.lankhorst, matthew.d.roper

On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> TileF(Tile4 in bspec) format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.

Why we still haven't done the F->tile64 rename?
This is the last chance to fix this before we bake 
this into the uapi and are stuck with a name that doesn't
match the spec and will just confuse everyone.

> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  3 ++
>  drivers/gpu/drm/i915/display/intel_fb.c       | 12 +++++-
>  drivers/gpu/drm/i915/display/intel_fbc.c      |  1 +
>  .../drm/i915/display/skl_universal_plane.c    | 37 ++++++++++++++-----
>  drivers/gpu/drm/i915/gem/i915_gem_object.h    |  8 +++-
>  drivers/gpu/drm/i915/gem/i915_gem_tiling.c    |  4 +-
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
>  drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
>  drivers/gpu/drm/i915/i915_drv.h               |  1 +
>  drivers/gpu/drm/i915/i915_pci.c               |  1 +
>  drivers/gpu/drm/i915/i915_reg.h               |  1 +
>  drivers/gpu/drm/i915/intel_device_info.h      |  1 +
>  drivers/gpu/drm/i915/intel_pm.c               |  1 +
>  include/uapi/drm/drm_fourcc.h                 |  8 ++++
>  include/uapi/drm/i915_drm.h                   |  3 +-
>  15 files changed, 71 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 23b1e0ccc72d..7564b8812c5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1335,6 +1335,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>  		break;
>  	case I915_TILING_X:
>  	case I915_TILING_Y:
> +	case I915_TILING_F:
>  		obj->tiling_and_stride =
>  			plane_config->fb->base.pitches[0] |
>  			plane_config->tiling;

I don't think tile64 supports fences so this shouldn't be here.

> @@ -1376,6 +1377,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_X_TILED:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_F_TILED:
>  		break;
>  	default:
>  		drm_dbg(&dev_priv->drm,
> @@ -9282,6 +9284,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
>  		case I915_FORMAT_MOD_X_TILED:
>  		case I915_FORMAT_MOD_Y_TILED:
>  		case I915_FORMAT_MOD_Yf_TILED:
> +		case I915_FORMAT_MOD_F_TILED:
>  			break;
>  		default:
>  			drm_dbg_kms(&i915->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e4b8602ec0cd..d88070406098 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -101,6 +101,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>  			return 128;
>  		else
>  			return 512;
> +	case I915_FORMAT_MOD_F_TILED:
> +		/*
> +		 * Each 4K tile consists of 64B(8*8) subtiles, with
> +		 * same shape as Y Tile(i.e 4*16B OWords)
> +		 */
> +		return 128;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  		if (is_ccs_plane(fb, color_plane))
>  			return 128;
> @@ -185,6 +191,8 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
>  	switch (fb_modifier) {
>  	case I915_FORMAT_MOD_X_TILED:
>  		return I915_TILING_X;
> +	case I915_FORMAT_MOD_F_TILED:
> +		return I915_TILING_F;

If there are no tile64 fences I915_TILING_F shouldn't even exist.

>  	case I915_FORMAT_MOD_Y_TILED:
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> @@ -264,6 +272,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Yf_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_F_TILED:
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return 1 * 1024 * 1024;
>  	default:
> @@ -1282,7 +1291,8 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  	} else {
>  		if (tiling == I915_TILING_X) {
>  			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
> -		} else if (tiling == I915_TILING_Y) {
> +		} else if ((tiling == I915_TILING_Y) ||
> +			   (tiling == I915_TILING_F)) {

This here is yet another fence related thing. Not relevant for tile64.

>  			drm_dbg_kms(&dev_priv->drm,
>  				    "No Y tiling for legacy addfb\n");
>  			goto err;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b1c1a23c36be..015005cf2ba1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -679,6 +679,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
>  	switch (modifier) {
>  	case DRM_FORMAT_MOD_LINEAR:
>  	case I915_FORMAT_MOD_Y_TILED:
> +	case I915_FORMAT_MOD_F_TILED:
>  		return DISPLAY_VER(dev_priv) >= 9;
>  	case I915_FORMAT_MOD_X_TILED:
>  		return true;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 724e7b04f3b6..09c00fc099f2 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -206,6 +206,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
>  	DRM_FORMAT_MOD_INVALID
>  };
>  
> +static const u64 dg2_plane_format_modifiers[] = {
> +	I915_FORMAT_MOD_X_TILED,
> +	I915_FORMAT_MOD_F_TILED,
> +	DRM_FORMAT_MOD_LINEAR,
> +	DRM_FORMAT_MOD_INVALID
> +};
> +
>  int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  {
>  	switch (format) {
> @@ -793,6 +800,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  		return PLANE_CTL_TILED_X;
>  	case I915_FORMAT_MOD_Y_TILED:
>  		return PLANE_CTL_TILED_Y;
> +	case I915_FORMAT_MOD_F_TILED:
> +		return PLANE_CTL_TILED_F;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1240,6 +1249,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> +	     fb->modifier == I915_FORMAT_MOD_F_TILED ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
>  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {

Seems like it would be much simpler to swap this around
to check for linear/X instead (+ adjust the debug message
to match).

> @@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			return false;
>  		break;
> +	case I915_FORMAT_MOD_F_TILED:
> +		if (!HAS_FTILE(dev_priv))
> +			return false;
> +		fallthrough;
>  	default:
>  		return false;
>  	}
> @@ -1981,9 +1995,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_Y216:
>  	case DRM_FORMAT_XVYU12_16161616:
>  	case DRM_FORMAT_XVYU16161616:
> -		if (modifier == DRM_FORMAT_MOD_LINEAR ||
> -		    modifier == I915_FORMAT_MOD_X_TILED ||
> -		    modifier == I915_FORMAT_MOD_Y_TILED)
> +		if (!is_ccs_modifier(modifier))
>  			return true;
>  		fallthrough;
>  	default:
> @@ -1994,8 +2006,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
>  static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
>  					    enum plane_id plane_id)
>  {
> +	if (HAS_FTILE(dev_priv))
> +		return dg2_plane_format_modifiers;
>  	/* Wa_22011186057 */
> -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> +	else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  		return adlp_step_a_plane_format_modifiers;
>  	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
>  		return gen12_plane_format_modifiers_mc_ccs;
> @@ -2265,11 +2279,16 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>  		else
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
> -	case PLANE_CTL_TILED_YF:
> -		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> -		else
> -			fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> +	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
> +		if (DISPLAY_VER(dev_priv) >= 13) {
> +			plane_config->tiling = I915_TILING_F;

Another fence related thing.

> +			fb->modifier = I915_FORMAT_MOD_F_TILED;
> +		} else {
> +			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> +			else
> +				fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> +		}
>  		break;
>  	default:
>  		MISSING_CASE(tiling);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index 3043fcbd31bd..d96bcab1f3e3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -326,7 +326,13 @@ static inline unsigned int
>  i915_gem_tile_height(unsigned int tiling)
>  {
>  	GEM_BUG_ON(!tiling);
> -	return tiling == I915_TILING_Y ? 32 : 8;
> +	switch (tiling) {
> +	case I915_TILING_Y:
> +	case I915_TILING_F:

Starting with this...

> +		return 32;
> +	default:
> +		return 8;
> +	}
>  }
>  
>  static inline unsigned int
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> index ef4d0f7dc118..520b8fb7c870 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> @@ -145,7 +145,8 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
>  	}
>  
>  	if (GRAPHICS_VER(i915) == 2 ||
> -	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
> +	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)) ||
> +	     tiling == I915_TILING_F)
>  		tile_width = 128;
>  	else
>  		tile_width = 512;
> @@ -438,6 +439,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
>  		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
>  		break;
>  	case I915_TILING_Y:
> +	case I915_TILING_F:
>  		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
>  		break;
>  	default:
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index f8948de72036..f748bcbf46c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -77,7 +77,8 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
>  		val <<= 32;
>  		val |= fence->start;
>  		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
> -		if (fence->tiling == I915_TILING_Y)
> +		if (fence->tiling == I915_TILING_Y ||
> +		    fence->tiling == I915_TILING_F)
>  			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
>  		val |= I965_FENCE_REG_VALID;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fdbd46ff59e0..f43968fc16fe 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -82,6 +82,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
>  	case I915_TILING_NONE: return ' ';
>  	case I915_TILING_X: return 'X';
>  	case I915_TILING_Y: return 'Y';
> +	case I915_TILING_F: return 'F';
>  	}

... ending here is all about fences. So should be dropped.

>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cc355aa05dbf..dafa8b1f365a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1586,6 +1586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
>  
>  #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
> +#define HAS_FTILE(dev_priv)    (INTEL_INFO(dev_priv)->has_ftile)
>  #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
>  #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
>  #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d4a6a9dcf182..81963d5876ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -970,6 +970,7 @@ static const struct intel_device_info adl_p_info = {
>  	.display.has_cdclk_crawl = 1,
>  	.display.has_modular_fia = 1,
>  	.display.has_psr_hw_tracking = 0,
> +	.has_ftile = 1, \
>  	.platform_engine_mask =
>  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>  	.ppgtt_size = 48,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cad84c3b864b..55c8a47ba047 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7192,6 +7192,7 @@ enum {
>  #define   PLANE_CTL_TILED_X			(1 << 10)
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
> +#define   PLANE_CTL_TILED_F			(5 << 10)
>  #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d328bb95c49b..76f783c10f81 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
>  	func(has_64bit_reloc); \
>  	func(gpu_reset_clobbers_display); \
>  	func(has_reset_engine); \
> +	func(has_ftile); \
>  	func(has_global_mocs); \
>  	func(has_gt_uc); \
>  	func(has_l3_dpf); \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 74fd6aa7afc7..6e68f259c4c1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5362,6 +5362,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
>  	}
>  
>  	wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> +		      modifier == I915_FORMAT_MOD_F_TILED ||
>  		      modifier == I915_FORMAT_MOD_Yf_TILED ||
>  		      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  		      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 45a914850be0..a7d3027b5bdc 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -558,6 +558,14 @@ extern "C" {
>   * pitch is required to be a multiple of 4 tile widths.
>   */
>  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +/*
> + * Intel F-tiling(aka Tile4) layout
> + *
> + * This is a tiled layout using 4Kb tiles in row-major layout.
> + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> + * (16 bytes) chunks column-major..
> + */
> +#define I915_FORMAT_MOD_F_TILED         fourcc_mod_code(INTEL, 10)
>  
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index bde5860b3686..d7dc421c6134 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
>  #define I915_TILING_NONE	0
>  #define I915_TILING_X		1
>  #define I915_TILING_Y		2
> -#define I915_TILING_LAST	I915_TILING_Y
> +#define I915_TILING_F		3
> +#define I915_TILING_LAST	I915_TILING_F

fences...

>  
>  #define I915_BIT_6_SWIZZLE_NONE		0
>  #define I915_BIT_6_SWIZZLE_9		1
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23 15:49 ` [Intel-gfx] [PATCH] " Ville Syrjälä
@ 2021-09-23 16:19   ` Lisovskiy, Stanislav
  2021-09-27 18:23   ` Matt Roper
  1 sibling, 0 replies; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-23 16:19 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: intel-gfx, jani.saarinen, maarten.lankhorst, matthew.d.roper

On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> 
> Why we still haven't done the F->tile64 rename?
> This is the last chance to fix this before we bake 
> this into the uapi and are stuck with a name that doesn't
> match the spec and will just confuse everyone.

Probably should be Tile4 then, currently we have Tile4 and Tile64
in BSpec and that one was about Tile4.

> 
> > 
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  3 ++
> >  drivers/gpu/drm/i915/display/intel_fb.c       | 12 +++++-
> >  drivers/gpu/drm/i915/display/intel_fbc.c      |  1 +
> >  .../drm/i915/display/skl_universal_plane.c    | 37 ++++++++++++++-----
> >  drivers/gpu/drm/i915/gem/i915_gem_object.h    |  8 +++-
> >  drivers/gpu/drm/i915/gem/i915_gem_tiling.c    |  4 +-
> >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
> >  drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
> >  drivers/gpu/drm/i915/i915_drv.h               |  1 +
> >  drivers/gpu/drm/i915/i915_pci.c               |  1 +
> >  drivers/gpu/drm/i915/i915_reg.h               |  1 +
> >  drivers/gpu/drm/i915/intel_device_info.h      |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c               |  1 +
> >  include/uapi/drm/drm_fourcc.h                 |  8 ++++
> >  include/uapi/drm/i915_drm.h                   |  3 +-
> >  15 files changed, 71 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 23b1e0ccc72d..7564b8812c5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1335,6 +1335,7 @@ initial_plane_vma(struct drm_i915_private *i915,
> >  		break;
> >  	case I915_TILING_X:
> >  	case I915_TILING_Y:
> > +	case I915_TILING_F:
> >  		obj->tiling_and_stride =
> >  			plane_config->fb->base.pitches[0] |
> >  			plane_config->tiling;
> 
> I don't think tile64 supports fences so this shouldn't be here.

Didn't find anything specific to Tile4, would prefer to recheck before
removing, in order to avoid unexpected breakages.

Stan

> 
> > @@ -1376,6 +1377,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
> >  	case DRM_FORMAT_MOD_LINEAR:
> >  	case I915_FORMAT_MOD_X_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED:
> > +	case I915_FORMAT_MOD_F_TILED:
> >  		break;
> >  	default:
> >  		drm_dbg(&dev_priv->drm,
> > @@ -9282,6 +9284,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
> >  		case I915_FORMAT_MOD_X_TILED:
> >  		case I915_FORMAT_MOD_Y_TILED:
> >  		case I915_FORMAT_MOD_Yf_TILED:
> > +		case I915_FORMAT_MOD_F_TILED:
> >  			break;
> >  		default:
> >  			drm_dbg_kms(&i915->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index e4b8602ec0cd..d88070406098 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -101,6 +101,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  			return 128;
> >  		else
> >  			return 512;
> > +	case I915_FORMAT_MOD_F_TILED:
> > +		/*
> > +		 * Each 4K tile consists of 64B(8*8) subtiles, with
> > +		 * same shape as Y Tile(i.e 4*16B OWords)
> > +		 */
> > +		return 128;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  		if (is_ccs_plane(fb, color_plane))
> >  			return 128;
> > @@ -185,6 +191,8 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> >  	switch (fb_modifier) {
> >  	case I915_FORMAT_MOD_X_TILED:
> >  		return I915_TILING_X;
> > +	case I915_FORMAT_MOD_F_TILED:
> > +		return I915_TILING_F;
> 
> If there are no tile64 fences I915_TILING_F shouldn't even exist.
> 
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > @@ -264,6 +272,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Yf_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED:
> > +	case I915_FORMAT_MOD_F_TILED:
> >  	case I915_FORMAT_MOD_Yf_TILED:
> >  		return 1 * 1024 * 1024;
> >  	default:
> > @@ -1282,7 +1291,8 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> >  	} else {
> >  		if (tiling == I915_TILING_X) {
> >  			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
> > -		} else if (tiling == I915_TILING_Y) {
> > +		} else if ((tiling == I915_TILING_Y) ||
> > +			   (tiling == I915_TILING_F)) {
> 
> This here is yet another fence related thing. Not relevant for tile64.
> 
> >  			drm_dbg_kms(&dev_priv->drm,
> >  				    "No Y tiling for legacy addfb\n");
> >  			goto err;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index b1c1a23c36be..015005cf2ba1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -679,6 +679,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
> >  	switch (modifier) {
> >  	case DRM_FORMAT_MOD_LINEAR:
> >  	case I915_FORMAT_MOD_Y_TILED:
> > +	case I915_FORMAT_MOD_F_TILED:
> >  		return DISPLAY_VER(dev_priv) >= 9;
> >  	case I915_FORMAT_MOD_X_TILED:
> >  		return true;
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 724e7b04f3b6..09c00fc099f2 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -206,6 +206,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
> >  	DRM_FORMAT_MOD_INVALID
> >  };
> >  
> > +static const u64 dg2_plane_format_modifiers[] = {
> > +	I915_FORMAT_MOD_X_TILED,
> > +	I915_FORMAT_MOD_F_TILED,
> > +	DRM_FORMAT_MOD_LINEAR,
> > +	DRM_FORMAT_MOD_INVALID
> > +};
> > +
> >  int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> >  {
> >  	switch (format) {
> > @@ -793,6 +800,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  		return PLANE_CTL_TILED_X;
> >  	case I915_FORMAT_MOD_Y_TILED:
> >  		return PLANE_CTL_TILED_Y;
> > +	case I915_FORMAT_MOD_F_TILED:
> > +		return PLANE_CTL_TILED_F;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1240,6 +1249,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
> > +	     fb->modifier == I915_FORMAT_MOD_F_TILED ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
> >  	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
> 
> Seems like it would be much simpler to swap this around
> to check for linear/X instead (+ adjust the debug message
> to match).
> 
> > @@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >  			return false;
> >  		break;
> > +	case I915_FORMAT_MOD_F_TILED:
> > +		if (!HAS_FTILE(dev_priv))
> > +			return false;
> > +		fallthrough;
> >  	default:
> >  		return false;
> >  	}
> > @@ -1981,9 +1995,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case DRM_FORMAT_Y216:
> >  	case DRM_FORMAT_XVYU12_16161616:
> >  	case DRM_FORMAT_XVYU16161616:
> > -		if (modifier == DRM_FORMAT_MOD_LINEAR ||
> > -		    modifier == I915_FORMAT_MOD_X_TILED ||
> > -		    modifier == I915_FORMAT_MOD_Y_TILED)
> > +		if (!is_ccs_modifier(modifier))
> >  			return true;
> >  		fallthrough;
> >  	default:
> > @@ -1994,8 +2006,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> >  static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> >  					    enum plane_id plane_id)
> >  {
> > +	if (HAS_FTILE(dev_priv))
> > +		return dg2_plane_format_modifiers;
> >  	/* Wa_22011186057 */
> > -	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > +	else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >  		return adlp_step_a_plane_format_modifiers;
> >  	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> >  		return gen12_plane_format_modifiers_mc_ccs;
> > @@ -2265,11 +2279,16 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> >  		else
> >  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
> >  		break;
> > -	case PLANE_CTL_TILED_YF:
> > -		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > -			fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > -		else
> > -			fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > +	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
> > +		if (DISPLAY_VER(dev_priv) >= 13) {
> > +			plane_config->tiling = I915_TILING_F;
> 
> Another fence related thing.
> 
> > +			fb->modifier = I915_FORMAT_MOD_F_TILED;
> > +		} else {
> > +			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > +				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
> > +			else
> > +				fb->modifier = I915_FORMAT_MOD_Yf_TILED;
> > +		}
> >  		break;
> >  	default:
> >  		MISSING_CASE(tiling);
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > index 3043fcbd31bd..d96bcab1f3e3 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> > @@ -326,7 +326,13 @@ static inline unsigned int
> >  i915_gem_tile_height(unsigned int tiling)
> >  {
> >  	GEM_BUG_ON(!tiling);
> > -	return tiling == I915_TILING_Y ? 32 : 8;
> > +	switch (tiling) {
> > +	case I915_TILING_Y:
> > +	case I915_TILING_F:
> 
> Starting with this...
> 
> > +		return 32;
> > +	default:
> > +		return 8;
> > +	}
> >  }
> >  
> >  static inline unsigned int
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> > index ef4d0f7dc118..520b8fb7c870 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
> > @@ -145,7 +145,8 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
> >  	}
> >  
> >  	if (GRAPHICS_VER(i915) == 2 ||
> > -	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
> > +	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)) ||
> > +	     tiling == I915_TILING_F)
> >  		tile_width = 128;
> >  	else
> >  		tile_width = 512;
> > @@ -438,6 +439,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
> >  		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
> >  		break;
> >  	case I915_TILING_Y:
> > +	case I915_TILING_F:
> >  		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
> >  		break;
> >  	default:
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > index f8948de72036..f748bcbf46c3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > @@ -77,7 +77,8 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
> >  		val <<= 32;
> >  		val |= fence->start;
> >  		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
> > -		if (fence->tiling == I915_TILING_Y)
> > +		if (fence->tiling == I915_TILING_Y ||
> > +		    fence->tiling == I915_TILING_F)
> >  			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
> >  		val |= I965_FENCE_REG_VALID;
> >  	}
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index fdbd46ff59e0..f43968fc16fe 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -82,6 +82,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
> >  	case I915_TILING_NONE: return ' ';
> >  	case I915_TILING_X: return 'X';
> >  	case I915_TILING_Y: return 'Y';
> > +	case I915_TILING_F: return 'F';
> >  	}
> 
> ... ending here is all about fences. So should be dropped.
> 
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index cc355aa05dbf..dafa8b1f365a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1586,6 +1586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >  #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> >  
> >  #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
> > +#define HAS_FTILE(dev_priv)    (INTEL_INFO(dev_priv)->has_ftile)
> >  #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
> >  #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
> >  #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index d4a6a9dcf182..81963d5876ef 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -970,6 +970,7 @@ static const struct intel_device_info adl_p_info = {
> >  	.display.has_cdclk_crawl = 1,
> >  	.display.has_modular_fia = 1,
> >  	.display.has_psr_hw_tracking = 0,
> > +	.has_ftile = 1, \
> >  	.platform_engine_mask =
> >  		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> >  	.ppgtt_size = 48,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index cad84c3b864b..55c8a47ba047 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7192,6 +7192,7 @@ enum {
> >  #define   PLANE_CTL_TILED_X			(1 << 10)
> >  #define   PLANE_CTL_TILED_Y			(4 << 10)
> >  #define   PLANE_CTL_TILED_YF			(5 << 10)
> > +#define   PLANE_CTL_TILED_F			(5 << 10)
> >  #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
> >  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
> >  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index d328bb95c49b..76f783c10f81 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -125,6 +125,7 @@ enum intel_ppgtt_type {
> >  	func(has_64bit_reloc); \
> >  	func(gpu_reset_clobbers_display); \
> >  	func(has_reset_engine); \
> > +	func(has_ftile); \
> >  	func(has_global_mocs); \
> >  	func(has_gt_uc); \
> >  	func(has_l3_dpf); \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 74fd6aa7afc7..6e68f259c4c1 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5362,6 +5362,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> >  	}
> >  
> >  	wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
> > +		      modifier == I915_FORMAT_MOD_F_TILED ||
> >  		      modifier == I915_FORMAT_MOD_Yf_TILED ||
> >  		      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >  		      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index 45a914850be0..a7d3027b5bdc 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -558,6 +558,14 @@ extern "C" {
> >   * pitch is required to be a multiple of 4 tile widths.
> >   */
> >  #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> > +/*
> > + * Intel F-tiling(aka Tile4) layout
> > + *
> > + * This is a tiled layout using 4Kb tiles in row-major layout.
> > + * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
> > + * (16 bytes) chunks column-major..
> > + */
> > +#define I915_FORMAT_MOD_F_TILED         fourcc_mod_code(INTEL, 10)
> >  
> >  /*
> >   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index bde5860b3686..d7dc421c6134 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> >  #define I915_TILING_NONE	0
> >  #define I915_TILING_X		1
> >  #define I915_TILING_Y		2
> > -#define I915_TILING_LAST	I915_TILING_Y
> > +#define I915_TILING_F		3
> > +#define I915_TILING_LAST	I915_TILING_F
> 
> fences...
> 
> >  
> >  #define I915_BIT_6_SWIZZLE_NONE		0
> >  #define I915_BIT_6_SWIZZLE_9		1
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-23 15:49 ` [Intel-gfx] [PATCH] " Ville Syrjälä
  2021-09-23 16:19   ` Lisovskiy, Stanislav
@ 2021-09-27 18:23   ` Matt Roper
  2021-09-27 18:29     ` Ville Syrjälä
  1 sibling, 1 reply; 18+ messages in thread
From: Matt Roper @ 2021-09-27 18:23 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Stanislav Lisovskiy, intel-gfx, jani.saarinen, maarten.lankhorst

On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > TileF(Tile4 in bspec) format is 4K tile organized into
> > 64B subtiles with same basic shape as for legacy TileY
> > which will be supported by Display13.
> 
> Why we still haven't done the F->tile64 rename?
>
> This is the last chance to fix this before we bake 
> this into the uapi and are stuck with a name that doesn't
> match the spec and will just confuse everyone.

I think you're confusing the formats here.  The bspec uses both terms
"TileF" and "Tile4" for the same format in different places.  There's a
completely different format that's referred to as both "TileS" and
"Tile64" in the bspec that we don't use at the moment.  So tile64
wouldn't be a correct rename, but tile4 could be.

In general Tile4 is much more common in the bspec than TileF is (TileF
terminology is mostly found in the media sections).  And bspec 44917 is
the most authoritative bspec page on the subject, and it refers to it as
Tile4, so I agree that switching over "Tile4" would probably be a good
move.

> 
> > 
...
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index bde5860b3686..d7dc421c6134 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> >  #define I915_TILING_NONE	0
> >  #define I915_TILING_X		1
> >  #define I915_TILING_Y		2
> > -#define I915_TILING_LAST	I915_TILING_Y
> > +#define I915_TILING_F		3
> > +#define I915_TILING_LAST	I915_TILING_F
> 
> fences...

Recognizing TileF/Tile4 separately from TileY is important to code
outside of display as well.  There are blitter instructions that require
different settings for TileY vs Tile4/F so if we drop the tracking of
this as a unique tiling type, it will break the blitting/copying and
some of the upcoming local memory support for Xe_HP-based platforms.


Matt

> 
> >  
> >  #define I915_BIT_6_SWIZZLE_NONE		0
> >  #define I915_BIT_6_SWIZZLE_9		1
> > -- 
> > 2.24.1.485.gad05a3d8e5
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-27 18:23   ` Matt Roper
@ 2021-09-27 18:29     ` Ville Syrjälä
  2021-09-28  5:24       ` Matt Roper
  0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2021-09-27 18:29 UTC (permalink / raw)
  To: Matt Roper
  Cc: Stanislav Lisovskiy, intel-gfx, jani.saarinen, maarten.lankhorst

On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > 64B subtiles with same basic shape as for legacy TileY
> > > which will be supported by Display13.
> > 
> > Why we still haven't done the F->tile64 rename?
> >
> > This is the last chance to fix this before we bake 
> > this into the uapi and are stuck with a name that doesn't
> > match the spec and will just confuse everyone.
> 
> I think you're confusing the formats here.  The bspec uses both terms
> "TileF" and "Tile4" for the same format in different places.  There's a
> completely different format that's referred to as both "TileS" and
> "Tile64" in the bspec that we don't use at the moment.  So tile64
> wouldn't be a correct rename, but tile4 could be.

Right, tile64 is the macro tile variant I think. So like Ys
which we never bothered implementing, so I guess we''l not bother
with tile64 either.

> 
> In general Tile4 is much more common in the bspec than TileF is (TileF
> terminology is mostly found in the media sections).  And bspec 44917 is
> the most authoritative bspec page on the subject, and it refers to it as
> Tile4, so I agree that switching over "Tile4" would probably be a good
> move.
> 
> > 
> > > 
> ...
> > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > index bde5860b3686..d7dc421c6134 100644
> > > --- a/include/uapi/drm/i915_drm.h
> > > +++ b/include/uapi/drm/i915_drm.h
> > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > >  #define I915_TILING_NONE	0
> > >  #define I915_TILING_X		1
> > >  #define I915_TILING_Y		2
> > > -#define I915_TILING_LAST	I915_TILING_Y
> > > +#define I915_TILING_F		3
> > > +#define I915_TILING_LAST	I915_TILING_F
> > 
> > fences...
> 
> Recognizing TileF/Tile4 separately from TileY is important to code
> outside of display as well.  There are blitter instructions that require
> different settings for TileY vs Tile4/F so if we drop the tracking of
> this as a unique tiling type, it will break the blitting/copying and
> some of the upcoming local memory support for Xe_HP-based platforms.

These are uapi definitions for set_tiling(). You are not meant to add
anything there. Just like we didn't add anything for Yf.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-27 18:29     ` Ville Syrjälä
@ 2021-09-28  5:24       ` Matt Roper
  2021-09-28 12:49         ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 18+ messages in thread
From: Matt Roper @ 2021-09-28  5:24 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Stanislav Lisovskiy, intel-gfx, jani.saarinen, maarten.lankhorst

On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > 64B subtiles with same basic shape as for legacy TileY
> > > > which will be supported by Display13.
> > > 
> > > Why we still haven't done the F->tile64 rename?
> > >
> > > This is the last chance to fix this before we bake 
> > > this into the uapi and are stuck with a name that doesn't
> > > match the spec and will just confuse everyone.
> > 
> > I think you're confusing the formats here.  The bspec uses both terms
> > "TileF" and "Tile4" for the same format in different places.  There's a
> > completely different format that's referred to as both "TileS" and
> > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > wouldn't be a correct rename, but tile4 could be.
> 
> Right, tile64 is the macro tile variant I think. So like Ys
> which we never bothered implementing, so I guess we''l not bother
> with tile64 either.
> 
> > 
> > In general Tile4 is much more common in the bspec than TileF is (TileF
> > terminology is mostly found in the media sections).  And bspec 44917 is
> > the most authoritative bspec page on the subject, and it refers to it as
> > Tile4, so I agree that switching over "Tile4" would probably be a good
> > move.
> > 
> > > 
> > > > 
> > ...
> > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > index bde5860b3686..d7dc421c6134 100644
> > > > --- a/include/uapi/drm/i915_drm.h
> > > > +++ b/include/uapi/drm/i915_drm.h
> > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > >  #define I915_TILING_NONE	0
> > > >  #define I915_TILING_X		1
> > > >  #define I915_TILING_Y		2
> > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > +#define I915_TILING_F		3
> > > > +#define I915_TILING_LAST	I915_TILING_F
> > > 
> > > fences...
> > 
> > Recognizing TileF/Tile4 separately from TileY is important to code
> > outside of display as well.  There are blitter instructions that require
> > different settings for TileY vs Tile4/F so if we drop the tracking of
> > this as a unique tiling type, it will break the blitting/copying and
> > some of the upcoming local memory support for Xe_HP-based platforms.
> 
> These are uapi definitions for set_tiling(). You are not meant to add
> anything there. Just like we didn't add anything for Yf.

Yeah, I think that's the real problem --- we define some values here in
the uapi header, but we also wind up using the same set of values for
driver-internal non-uapi purposes too rather than having a separate enum
(containing a superset of the uapi values) that can be used for those
other things.  Display code can use FB modifiers for some things, but
core/lmem code needs a way to refer to Tile4 and such and doesn't have a
good way to do that today.

I think most (all?) of the non-display code that's relying on a
definition of I915_TILING_F is in various selftests that are still being
prepared for upstreaming, so maybe there's a better way to handle the
selection of possible formats specifically in the selftest code itself.
That's really the only area of the kernel code that should need to be
aware of the specific internal layout of various buffers.


Matt

> 
> -- 
> Ville Syrjälä
> Intel

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-28  5:24       ` Matt Roper
@ 2021-09-28 12:49         ` Lisovskiy, Stanislav
  2021-09-28 19:02           ` Ville Syrjälä
  0 siblings, 1 reply; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-28 12:49 UTC (permalink / raw)
  To: Matt Roper
  Cc: Ville Syrjälä, intel-gfx, jani.saarinen, maarten.lankhorst

On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote:
> On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > which will be supported by Display13.
> > > > 
> > > > Why we still haven't done the F->tile64 rename?
> > > >
> > > > This is the last chance to fix this before we bake 
> > > > this into the uapi and are stuck with a name that doesn't
> > > > match the spec and will just confuse everyone.
> > > 
> > > I think you're confusing the formats here.  The bspec uses both terms
> > > "TileF" and "Tile4" for the same format in different places.  There's a
> > > completely different format that's referred to as both "TileS" and
> > > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > > wouldn't be a correct rename, but tile4 could be.
> > 
> > Right, tile64 is the macro tile variant I think. So like Ys
> > which we never bothered implementing, so I guess we''l not bother
> > with tile64 either.
> > 
> > > 
> > > In general Tile4 is much more common in the bspec than TileF is (TileF
> > > terminology is mostly found in the media sections).  And bspec 44917 is
> > > the most authoritative bspec page on the subject, and it refers to it as
> > > Tile4, so I agree that switching over "Tile4" would probably be a good
> > > move.
> > > 
> > > > 
> > > > > 
> > > ...
> > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > index bde5860b3686..d7dc421c6134 100644
> > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > > >  #define I915_TILING_NONE	0
> > > > >  #define I915_TILING_X		1
> > > > >  #define I915_TILING_Y		2
> > > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > > +#define I915_TILING_F		3
> > > > > +#define I915_TILING_LAST	I915_TILING_F
> > > > 
> > > > fences...
> > > 
> > > Recognizing TileF/Tile4 separately from TileY is important to code
> > > outside of display as well.  There are blitter instructions that require
> > > different settings for TileY vs Tile4/F so if we drop the tracking of
> > > this as a unique tiling type, it will break the blitting/copying and
> > > some of the upcoming local memory support for Xe_HP-based platforms.
> > 
> > These are uapi definitions for set_tiling(). You are not meant to add
> > anything there. Just like we didn't add anything for Yf.
> 
> Yeah, I think that's the real problem --- we define some values here in
> the uapi header, but we also wind up using the same set of values for
> driver-internal non-uapi purposes too rather than having a separate enum
> (containing a superset of the uapi values) that can be used for those
> other things.  Display code can use FB modifiers for some things, but
> core/lmem code needs a way to refer to Tile4 and such and doesn't have a
> good way to do that today.
> 
> I think most (all?) of the non-display code that's relying on a
> definition of I915_TILING_F is in various selftests that are still being
> prepared for upstreaming, so maybe there's a better way to handle the
> selection of possible formats specifically in the selftest code itself.
> That's really the only area of the kernel code that should need to be
> aware of the specific internal layout of various buffers.

So I will proceed with the renaming at least.

Ville, suppose, I still need part of fencing related code?

Stan

> 
> 
> Matt
> 
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-28 12:49         ` Lisovskiy, Stanislav
@ 2021-09-28 19:02           ` Ville Syrjälä
  2021-09-28 20:36             ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2021-09-28 19:02 UTC (permalink / raw)
  To: Lisovskiy, Stanislav
  Cc: Matt Roper, intel-gfx, jani.saarinen, maarten.lankhorst

On Tue, Sep 28, 2021 at 03:49:11PM +0300, Lisovskiy, Stanislav wrote:
> On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote:
> > On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> > > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > which will be supported by Display13.
> > > > > 
> > > > > Why we still haven't done the F->tile64 rename?
> > > > >
> > > > > This is the last chance to fix this before we bake 
> > > > > this into the uapi and are stuck with a name that doesn't
> > > > > match the spec and will just confuse everyone.
> > > > 
> > > > I think you're confusing the formats here.  The bspec uses both terms
> > > > "TileF" and "Tile4" for the same format in different places.  There's a
> > > > completely different format that's referred to as both "TileS" and
> > > > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > > > wouldn't be a correct rename, but tile4 could be.
> > > 
> > > Right, tile64 is the macro tile variant I think. So like Ys
> > > which we never bothered implementing, so I guess we''l not bother
> > > with tile64 either.
> > > 
> > > > 
> > > > In general Tile4 is much more common in the bspec than TileF is (TileF
> > > > terminology is mostly found in the media sections).  And bspec 44917 is
> > > > the most authoritative bspec page on the subject, and it refers to it as
> > > > Tile4, so I agree that switching over "Tile4" would probably be a good
> > > > move.
> > > > 
> > > > > 
> > > > > > 
> > > > ...
> > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > > index bde5860b3686..d7dc421c6134 100644
> > > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > > > >  #define I915_TILING_NONE	0
> > > > > >  #define I915_TILING_X		1
> > > > > >  #define I915_TILING_Y		2
> > > > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > > > +#define I915_TILING_F		3
> > > > > > +#define I915_TILING_LAST	I915_TILING_F
> > > > > 
> > > > > fences...
> > > > 
> > > > Recognizing TileF/Tile4 separately from TileY is important to code
> > > > outside of display as well.  There are blitter instructions that require
> > > > different settings for TileY vs Tile4/F so if we drop the tracking of
> > > > this as a unique tiling type, it will break the blitting/copying and
> > > > some of the upcoming local memory support for Xe_HP-based platforms.
> > > 
> > > These are uapi definitions for set_tiling(). You are not meant to add
> > > anything there. Just like we didn't add anything for Yf.
> > 
> > Yeah, I think that's the real problem --- we define some values here in
> > the uapi header, but we also wind up using the same set of values for
> > driver-internal non-uapi purposes too rather than having a separate enum
> > (containing a superset of the uapi values) that can be used for those
> > other things.  Display code can use FB modifiers for some things, but
> > core/lmem code needs a way to refer to Tile4 and such and doesn't have a
> > good way to do that today.
> > 
> > I think most (all?) of the non-display code that's relying on a
> > definition of I915_TILING_F is in various selftests that are still being
> > prepared for upstreaming, so maybe there's a better way to handle the
> > selection of possible formats specifically in the selftest code itself.
> > That's really the only area of the kernel code that should need to be
> > aware of the specific internal layout of various buffers.
> 
> So I will proceed with the renaming at least.
> 
> Ville, suppose, I still need part of fencing related code?

Nah. Just nuke it all. Someone will have to fix whatever self test is
abusing the uapi definitions though.

A local #define should suffice if nothing else is deemed appropriate.
IIRC igt also has a local definition like this for Yf. We should
perhaps rename those to some igt specific namespace as well...

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-28 19:02           ` Ville Syrjälä
@ 2021-09-28 20:36             ` Lisovskiy, Stanislav
  2021-09-28 20:47               ` Ville Syrjälä
  0 siblings, 1 reply; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-28 20:36 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Matt Roper, intel-gfx, jani.saarinen, maarten.lankhorst

On Tue, Sep 28, 2021 at 10:02:34PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 28, 2021 at 03:49:11PM +0300, Lisovskiy, Stanislav wrote:
> > On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote:
> > > On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> > > > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > > > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > > which will be supported by Display13.
> > > > > > 
> > > > > > Why we still haven't done the F->tile64 rename?
> > > > > >
> > > > > > This is the last chance to fix this before we bake 
> > > > > > this into the uapi and are stuck with a name that doesn't
> > > > > > match the spec and will just confuse everyone.
> > > > > 
> > > > > I think you're confusing the formats here.  The bspec uses both terms
> > > > > "TileF" and "Tile4" for the same format in different places.  There's a
> > > > > completely different format that's referred to as both "TileS" and
> > > > > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > > > > wouldn't be a correct rename, but tile4 could be.
> > > > 
> > > > Right, tile64 is the macro tile variant I think. So like Ys
> > > > which we never bothered implementing, so I guess we''l not bother
> > > > with tile64 either.
> > > > 
> > > > > 
> > > > > In general Tile4 is much more common in the bspec than TileF is (TileF
> > > > > terminology is mostly found in the media sections).  And bspec 44917 is
> > > > > the most authoritative bspec page on the subject, and it refers to it as
> > > > > Tile4, so I agree that switching over "Tile4" would probably be a good
> > > > > move.
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > ...
> > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > > > index bde5860b3686..d7dc421c6134 100644
> > > > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > > > > >  #define I915_TILING_NONE	0
> > > > > > >  #define I915_TILING_X		1
> > > > > > >  #define I915_TILING_Y		2
> > > > > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > > > > +#define I915_TILING_F		3
> > > > > > > +#define I915_TILING_LAST	I915_TILING_F
> > > > > > 
> > > > > > fences...
> > > > > 
> > > > > Recognizing TileF/Tile4 separately from TileY is important to code
> > > > > outside of display as well.  There are blitter instructions that require
> > > > > different settings for TileY vs Tile4/F so if we drop the tracking of
> > > > > this as a unique tiling type, it will break the blitting/copying and
> > > > > some of the upcoming local memory support for Xe_HP-based platforms.
> > > > 
> > > > These are uapi definitions for set_tiling(). You are not meant to add
> > > > anything there. Just like we didn't add anything for Yf.
> > > 
> > > Yeah, I think that's the real problem --- we define some values here in
> > > the uapi header, but we also wind up using the same set of values for
> > > driver-internal non-uapi purposes too rather than having a separate enum
> > > (containing a superset of the uapi values) that can be used for those
> > > other things.  Display code can use FB modifiers for some things, but
> > > core/lmem code needs a way to refer to Tile4 and such and doesn't have a
> > > good way to do that today.
> > > 
> > > I think most (all?) of the non-display code that's relying on a
> > > definition of I915_TILING_F is in various selftests that are still being
> > > prepared for upstreaming, so maybe there's a better way to handle the
> > > selection of possible formats specifically in the selftest code itself.
> > > That's really the only area of the kernel code that should need to be
> > > aware of the specific internal layout of various buffers.
> > 
> > So I will proceed with the renaming at least.
> > 
> > Ville, suppose, I still need part of fencing related code?
> 
> Nah. Just nuke it all. Someone will have to fix whatever self test is
> abusing the uapi definitions though.
> 
> A local #define should suffice if nothing else is deemed appropriate.
> IIRC igt also has a local definition like this for Yf. We should
> perhaps rename those to some igt specific namespace as well...

As Matt mentioned, removing I915_TILING_F completely is going to break
way more than selftest, but also blitter/copy and local mem support.
In fact I remember, I had to add part of those in order to get some
tests working, another part was added by somebody else, so not even
sure how much other stuff its going to break.

Sounds like a bit too much for simple upstreaming of the patch, we
already had internally for more than a year, just wondering why 
this popped up only by now.

Stan

> 
> -- 
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-28 20:36             ` Lisovskiy, Stanislav
@ 2021-09-28 20:47               ` Ville Syrjälä
  2021-09-29  6:15                 ` Lisovskiy, Stanislav
  0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2021-09-28 20:47 UTC (permalink / raw)
  To: Lisovskiy, Stanislav
  Cc: Matt Roper, intel-gfx, jani.saarinen, maarten.lankhorst

On Tue, Sep 28, 2021 at 11:36:51PM +0300, Lisovskiy, Stanislav wrote:
> On Tue, Sep 28, 2021 at 10:02:34PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 28, 2021 at 03:49:11PM +0300, Lisovskiy, Stanislav wrote:
> > > On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote:
> > > > On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> > > > > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > > > > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > > > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > > > which will be supported by Display13.
> > > > > > > 
> > > > > > > Why we still haven't done the F->tile64 rename?
> > > > > > >
> > > > > > > This is the last chance to fix this before we bake 
> > > > > > > this into the uapi and are stuck with a name that doesn't
> > > > > > > match the spec and will just confuse everyone.
> > > > > > 
> > > > > > I think you're confusing the formats here.  The bspec uses both terms
> > > > > > "TileF" and "Tile4" for the same format in different places.  There's a
> > > > > > completely different format that's referred to as both "TileS" and
> > > > > > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > > > > > wouldn't be a correct rename, but tile4 could be.
> > > > > 
> > > > > Right, tile64 is the macro tile variant I think. So like Ys
> > > > > which we never bothered implementing, so I guess we''l not bother
> > > > > with tile64 either.
> > > > > 
> > > > > > 
> > > > > > In general Tile4 is much more common in the bspec than TileF is (TileF
> > > > > > terminology is mostly found in the media sections).  And bspec 44917 is
> > > > > > the most authoritative bspec page on the subject, and it refers to it as
> > > > > > Tile4, so I agree that switching over "Tile4" would probably be a good
> > > > > > move.
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > ...
> > > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > > > > index bde5860b3686..d7dc421c6134 100644
> > > > > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > > > > > >  #define I915_TILING_NONE	0
> > > > > > > >  #define I915_TILING_X		1
> > > > > > > >  #define I915_TILING_Y		2
> > > > > > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > > > > > +#define I915_TILING_F		3
> > > > > > > > +#define I915_TILING_LAST	I915_TILING_F
> > > > > > > 
> > > > > > > fences...
> > > > > > 
> > > > > > Recognizing TileF/Tile4 separately from TileY is important to code
> > > > > > outside of display as well.  There are blitter instructions that require
> > > > > > different settings for TileY vs Tile4/F so if we drop the tracking of
> > > > > > this as a unique tiling type, it will break the blitting/copying and
> > > > > > some of the upcoming local memory support for Xe_HP-based platforms.
> > > > > 
> > > > > These are uapi definitions for set_tiling(). You are not meant to add
> > > > > anything there. Just like we didn't add anything for Yf.
> > > > 
> > > > Yeah, I think that's the real problem --- we define some values here in
> > > > the uapi header, but we also wind up using the same set of values for
> > > > driver-internal non-uapi purposes too rather than having a separate enum
> > > > (containing a superset of the uapi values) that can be used for those
> > > > other things.  Display code can use FB modifiers for some things, but
> > > > core/lmem code needs a way to refer to Tile4 and such and doesn't have a
> > > > good way to do that today.
> > > > 
> > > > I think most (all?) of the non-display code that's relying on a
> > > > definition of I915_TILING_F is in various selftests that are still being
> > > > prepared for upstreaming, so maybe there's a better way to handle the
> > > > selection of possible formats specifically in the selftest code itself.
> > > > That's really the only area of the kernel code that should need to be
> > > > aware of the specific internal layout of various buffers.
> > > 
> > > So I will proceed with the renaming at least.
> > > 
> > > Ville, suppose, I still need part of fencing related code?
> > 
> > Nah. Just nuke it all. Someone will have to fix whatever self test is
> > abusing the uapi definitions though.
> > 
> > A local #define should suffice if nothing else is deemed appropriate.
> > IIRC igt also has a local definition like this for Yf. We should
> > perhaps rename those to some igt specific namespace as well...
> 
> As Matt mentioned, removing I915_TILING_F completely is going to break
> way more than selftest, but also blitter/copy and local mem support.

No. The only non-fence use of I915_TILING_F I see is a blitter self test
of some sort.

> In fact I remember, I had to add part of those in order to get some
> tests working, another part was added by somebody else, so not even
> sure how much other stuff its going to break.
> 
> Sounds like a bit too much for simple upstreaming of the patch, we
> already had internally for more than a year, just wondering why 
> this popped up only by now.

Because someone tried to sneak in gem uapi additions under the
cover of darkness? All gem changes must be cc:dri-devel btw,
uapi doubly so. Oh, and drm_fourcc.h changes really need to go
there too.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
  2021-09-28 20:47               ` Ville Syrjälä
@ 2021-09-29  6:15                 ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 18+ messages in thread
From: Lisovskiy, Stanislav @ 2021-09-29  6:15 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: Matt Roper, intel-gfx, jani.saarinen, maarten.lankhorst

On Tue, Sep 28, 2021 at 11:47:51PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 28, 2021 at 11:36:51PM +0300, Lisovskiy, Stanislav wrote:
> > On Tue, Sep 28, 2021 at 10:02:34PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 28, 2021 at 03:49:11PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Mon, Sep 27, 2021 at 10:24:11PM -0700, Matt Roper wrote:
> > > > > On Mon, Sep 27, 2021 at 09:29:07PM +0300, Ville Syrjälä wrote:
> > > > > > On Mon, Sep 27, 2021 at 11:23:35AM -0700, Matt Roper wrote:
> > > > > > > On Thu, Sep 23, 2021 at 06:49:59PM +0300, Ville Syrjälä wrote:
> > > > > > > > On Thu, Sep 23, 2021 at 11:48:58AM +0300, Stanislav Lisovskiy wrote:
> > > > > > > > > TileF(Tile4 in bspec) format is 4K tile organized into
> > > > > > > > > 64B subtiles with same basic shape as for legacy TileY
> > > > > > > > > which will be supported by Display13.
> > > > > > > > 
> > > > > > > > Why we still haven't done the F->tile64 rename?
> > > > > > > >
> > > > > > > > This is the last chance to fix this before we bake 
> > > > > > > > this into the uapi and are stuck with a name that doesn't
> > > > > > > > match the spec and will just confuse everyone.
> > > > > > > 
> > > > > > > I think you're confusing the formats here.  The bspec uses both terms
> > > > > > > "TileF" and "Tile4" for the same format in different places.  There's a
> > > > > > > completely different format that's referred to as both "TileS" and
> > > > > > > "Tile64" in the bspec that we don't use at the moment.  So tile64
> > > > > > > wouldn't be a correct rename, but tile4 could be.
> > > > > > 
> > > > > > Right, tile64 is the macro tile variant I think. So like Ys
> > > > > > which we never bothered implementing, so I guess we''l not bother
> > > > > > with tile64 either.
> > > > > > 
> > > > > > > 
> > > > > > > In general Tile4 is much more common in the bspec than TileF is (TileF
> > > > > > > terminology is mostly found in the media sections).  And bspec 44917 is
> > > > > > > the most authoritative bspec page on the subject, and it refers to it as
> > > > > > > Tile4, so I agree that switching over "Tile4" would probably be a good
> > > > > > > move.
> > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > ...
> > > > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > > > > > > > > index bde5860b3686..d7dc421c6134 100644
> > > > > > > > > --- a/include/uapi/drm/i915_drm.h
> > > > > > > > > +++ b/include/uapi/drm/i915_drm.h
> > > > > > > > > @@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
> > > > > > > > >  #define I915_TILING_NONE	0
> > > > > > > > >  #define I915_TILING_X		1
> > > > > > > > >  #define I915_TILING_Y		2
> > > > > > > > > -#define I915_TILING_LAST	I915_TILING_Y
> > > > > > > > > +#define I915_TILING_F		3
> > > > > > > > > +#define I915_TILING_LAST	I915_TILING_F
> > > > > > > > 
> > > > > > > > fences...
> > > > > > > 
> > > > > > > Recognizing TileF/Tile4 separately from TileY is important to code
> > > > > > > outside of display as well.  There are blitter instructions that require
> > > > > > > different settings for TileY vs Tile4/F so if we drop the tracking of
> > > > > > > this as a unique tiling type, it will break the blitting/copying and
> > > > > > > some of the upcoming local memory support for Xe_HP-based platforms.
> > > > > > 
> > > > > > These are uapi definitions for set_tiling(). You are not meant to add
> > > > > > anything there. Just like we didn't add anything for Yf.
> > > > > 
> > > > > Yeah, I think that's the real problem --- we define some values here in
> > > > > the uapi header, but we also wind up using the same set of values for
> > > > > driver-internal non-uapi purposes too rather than having a separate enum
> > > > > (containing a superset of the uapi values) that can be used for those
> > > > > other things.  Display code can use FB modifiers for some things, but
> > > > > core/lmem code needs a way to refer to Tile4 and such and doesn't have a
> > > > > good way to do that today.
> > > > > 
> > > > > I think most (all?) of the non-display code that's relying on a
> > > > > definition of I915_TILING_F is in various selftests that are still being
> > > > > prepared for upstreaming, so maybe there's a better way to handle the
> > > > > selection of possible formats specifically in the selftest code itself.
> > > > > That's really the only area of the kernel code that should need to be
> > > > > aware of the specific internal layout of various buffers.
> > > > 
> > > > So I will proceed with the renaming at least.
> > > > 
> > > > Ville, suppose, I still need part of fencing related code?
> > > 
> > > Nah. Just nuke it all. Someone will have to fix whatever self test is
> > > abusing the uapi definitions though.
> > > 
> > > A local #define should suffice if nothing else is deemed appropriate.
> > > IIRC igt also has a local definition like this for Yf. We should
> > > perhaps rename those to some igt specific namespace as well...
> > 
> > As Matt mentioned, removing I915_TILING_F completely is going to break
> > way more than selftest, but also blitter/copy and local mem support.
> 
> No. The only non-fence use of I915_TILING_F I see is a blitter self test
> of some sort.
> 
> > In fact I remember, I had to add part of those in order to get some
> > tests working, another part was added by somebody else, so not even
> > sure how much other stuff its going to break.
> > 
> > Sounds like a bit too much for simple upstreaming of the patch, we
> > already had internally for more than a year, just wondering why 
> > this popped up only by now.
> 
> Because someone tried to sneak in gem uapi additions under the
> cover of darkness? All gem changes must be cc:dri-devel btw,
> uapi doubly so. Oh, and drm_fourcc.h changes really need to go
> there too.

I assume "internal" is "darkness" here? :)

What I actually meant is that, we could avoid all those issues and
danger of breaking the existing stuff, if all of that was discussed
in the very beginning.
To be honest, I wasn't aware of that kind of rules, my idea was just
to add I915_TILING_* just same way as it exists in the current code,
like I915_TILING_X/Y, because it seems "kind of" logical.

Otherwise for sure, something else would have been done.

Moreover after this patch has been pushed to internal and I even stopped
following what was happening with it to be honest, as it was already 
edited by multiple people and grew lots of other changes, I'm completely 
unaware of.

So what I just want to emphasize here, is that we should have had those
discussions one year ago and probably throughout the whole year when
this patch has been edited, not in the very last moment when it goes
to upstream - that way we would just avoid _more_ "wrong" changes coming
and now I'll have to sort out all this mess, instread of investigating more
urgent problems, we currently have.

Stan


> 
> -- 
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH] drm/i915: Tile F plane format support
@ 2021-09-23 13:17 Stanislav Lisovskiy
  0 siblings, 0 replies; 18+ messages in thread
From: Stanislav Lisovskiy @ 2021-09-23 13:17 UTC (permalink / raw)
  To: intel-gfx
  Cc: Stanislav.Lisovskiy, jani.saarinen, maarten.lankhorst, matthew.d.roper

TileF(Tile4 in bspec) format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.

v2: - Fixed wrong case condition(Jani Nikula)
    - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  3 ++
 drivers/gpu/drm/i915/display/intel_fb.c       | 12 +++++-
 drivers/gpu/drm/i915/display/intel_fbc.c      |  1 +
 .../drm/i915/display/skl_universal_plane.c    | 37 ++++++++++++++-----
 drivers/gpu/drm/i915/gem/i915_gem_object.h    |  8 +++-
 drivers/gpu/drm/i915/gem/i915_gem_tiling.c    |  4 +-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/i915_pci.c               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 drivers/gpu/drm/i915/intel_device_info.h      |  1 +
 drivers/gpu/drm/i915/intel_pm.c               |  1 +
 include/uapi/drm/drm_fourcc.h                 |  8 ++++
 include/uapi/drm/i915_drm.h                   |  3 +-
 15 files changed, 71 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 23b1e0ccc72d..7564b8812c5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1335,6 +1335,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 		break;
 	case I915_TILING_X:
 	case I915_TILING_Y:
+	case I915_TILING_F:
 		obj->tiling_and_stride =
 			plane_config->fb->base.pitches[0] |
 			plane_config->tiling;
@@ -1376,6 +1377,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_X_TILED:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 		break;
 	default:
 		drm_dbg(&dev_priv->drm,
@@ -9282,6 +9284,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state)
 		case I915_FORMAT_MOD_X_TILED:
 		case I915_FORMAT_MOD_Y_TILED:
 		case I915_FORMAT_MOD_Yf_TILED:
+		case I915_FORMAT_MOD_F_TILED:
 			break;
 		default:
 			drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index e4b8602ec0cd..d88070406098 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -101,6 +101,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		else
 			return 512;
+	case I915_FORMAT_MOD_F_TILED:
+		/*
+		 * Each 4K tile consists of 64B(8*8) subtiles, with
+		 * same shape as Y Tile(i.e 4*16B OWords)
+		 */
+		return 128;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 		if (is_ccs_plane(fb, color_plane))
 			return 128;
@@ -185,6 +191,8 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 	switch (fb_modifier) {
 	case I915_FORMAT_MOD_X_TILED:
 		return I915_TILING_X;
+	case I915_FORMAT_MOD_F_TILED:
+		return I915_TILING_F;
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
@@ -264,6 +272,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Yf_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
 		return 1 * 1024 * 1024;
 	default:
@@ -1282,7 +1291,8 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 	} else {
 		if (tiling == I915_TILING_X) {
 			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
-		} else if (tiling == I915_TILING_Y) {
+		} else if ((tiling == I915_TILING_Y) ||
+			   (tiling == I915_TILING_F)) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "No Y tiling for legacy addfb\n");
 			goto err;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b1c1a23c36be..015005cf2ba1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -679,6 +679,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 	switch (modifier) {
 	case DRM_FORMAT_MOD_LINEAR:
 	case I915_FORMAT_MOD_Y_TILED:
+	case I915_FORMAT_MOD_F_TILED:
 		return DISPLAY_VER(dev_priv) >= 9;
 	case I915_FORMAT_MOD_X_TILED:
 		return true;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b6..3dfb474498c8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -206,6 +206,13 @@ static const u64 adlp_step_a_plane_format_modifiers[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
+static const u64 dg2_plane_format_modifiers[] = {
+	I915_FORMAT_MOD_X_TILED,
+	I915_FORMAT_MOD_F_TILED,
+	DRM_FORMAT_MOD_LINEAR,
+	DRM_FORMAT_MOD_INVALID
+};
+
 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
 	switch (format) {
@@ -793,6 +800,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_X;
 	case I915_FORMAT_MOD_Y_TILED:
 		return PLANE_CTL_TILED_Y;
+	case I915_FORMAT_MOD_F_TILED:
+		return PLANE_CTL_TILED_F;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1240,6 +1249,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+	     fb->modifier == I915_FORMAT_MOD_F_TILED ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
 	     fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
@@ -1941,6 +1951,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			return false;
 		break;
+	case I915_FORMAT_MOD_F_TILED:
+		if (!HAS_FTILE(dev_priv))
+			return false;
+		break;
 	default:
 		return false;
 	}
@@ -1981,9 +1995,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_Y216:
 	case DRM_FORMAT_XVYU12_16161616:
 	case DRM_FORMAT_XVYU16161616:
-		if (modifier == DRM_FORMAT_MOD_LINEAR ||
-		    modifier == I915_FORMAT_MOD_X_TILED ||
-		    modifier == I915_FORMAT_MOD_Y_TILED)
+		if (!is_ccs_modifier(modifier))
 			return true;
 		fallthrough;
 	default:
@@ -1994,8 +2006,10 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
 static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
 					    enum plane_id plane_id)
 {
+	if (HAS_FTILE(dev_priv))
+		return dg2_plane_format_modifiers;
 	/* Wa_22011186057 */
-	if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+	else if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 		return adlp_step_a_plane_format_modifiers;
 	else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
 		return gen12_plane_format_modifiers_mc_ccs;
@@ -2265,11 +2279,16 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 		else
 			fb->modifier = I915_FORMAT_MOD_Y_TILED;
 		break;
-	case PLANE_CTL_TILED_YF:
-		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
-		else
-			fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_F on XE_LPD+ */
+		if (DISPLAY_VER(dev_priv) >= 13) {
+			plane_config->tiling = I915_TILING_F;
+			fb->modifier = I915_FORMAT_MOD_F_TILED;
+		} else {
+			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+			else
+				fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+		}
 		break;
 	default:
 		MISSING_CASE(tiling);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 3043fcbd31bd..d96bcab1f3e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -326,7 +326,13 @@ static inline unsigned int
 i915_gem_tile_height(unsigned int tiling)
 {
 	GEM_BUG_ON(!tiling);
-	return tiling == I915_TILING_Y ? 32 : 8;
+	switch (tiling) {
+	case I915_TILING_Y:
+	case I915_TILING_F:
+		return 32;
+	default:
+		return 8;
+	}
 }
 
 static inline unsigned int
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ef4d0f7dc118..520b8fb7c870 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -145,7 +145,8 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
 	}
 
 	if (GRAPHICS_VER(i915) == 2 ||
-	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
+	    (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)) ||
+	     tiling == I915_TILING_F)
 		tile_width = 128;
 	else
 		tile_width = 512;
@@ -438,6 +439,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_x;
 		break;
 	case I915_TILING_Y:
+	case I915_TILING_F:
 		args->swizzle_mode = dev_priv->ggtt.bit_6_swizzle_y;
 		break;
 	default:
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f8948de72036..f748bcbf46c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -77,7 +77,8 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
 		val <<= 32;
 		val |= fence->start;
 		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
-		if (fence->tiling == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y ||
+		    fence->tiling == I915_TILING_F)
 			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 		val |= I965_FENCE_REG_VALID;
 	}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdbd46ff59e0..f43968fc16fe 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -82,6 +82,7 @@ static char get_tiling_flag(struct drm_i915_gem_object *obj)
 	case I915_TILING_NONE: return ' ';
 	case I915_TILING_X: return 'X';
 	case I915_TILING_Y: return 'Y';
+	case I915_TILING_F: return 'F';
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cc355aa05dbf..dafa8b1f365a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1586,6 +1586,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 
 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
+#define HAS_FTILE(dev_priv)    (INTEL_INFO(dev_priv)->has_ftile)
 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d4a6a9dcf182..81963d5876ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -970,6 +970,7 @@ static const struct intel_device_info adl_p_info = {
 	.display.has_cdclk_crawl = 1,
 	.display.has_modular_fia = 1,
 	.display.has_psr_hw_tracking = 0,
+	.has_ftile = 1, \
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.ppgtt_size = 48,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cad84c3b864b..55c8a47ba047 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,6 +7192,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_TILED_F			(5 << 10)
 #define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d328bb95c49b..76f783c10f81 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,7 @@ enum intel_ppgtt_type {
 	func(has_64bit_reloc); \
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
+	func(has_ftile); \
 	func(has_global_mocs); \
 	func(has_gt_uc); \
 	func(has_l3_dpf); \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 74fd6aa7afc7..6e68f259c4c1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5362,6 +5362,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 	}
 
 	wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+		      modifier == I915_FORMAT_MOD_F_TILED ||
 		      modifier == I915_FORMAT_MOD_Yf_TILED ||
 		      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 		      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 45a914850be0..f97c9bd5d47d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -558,6 +558,14 @@ extern "C" {
  * pitch is required to be a multiple of 4 tile widths.
  */
 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
+/*
+ * Intel F-tiling(aka Tile4) layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
+ * (16 bytes) chunks column-major..
+ */
+#define I915_FORMAT_MOD_F_TILED         fourcc_mod_code(INTEL, 12)
 
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index bde5860b3686..d7dc421c6134 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1522,7 +1522,8 @@ struct drm_i915_gem_caching {
 #define I915_TILING_NONE	0
 #define I915_TILING_X		1
 #define I915_TILING_Y		2
-#define I915_TILING_LAST	I915_TILING_Y
+#define I915_TILING_F		3
+#define I915_TILING_LAST	I915_TILING_F
 
 #define I915_BIT_6_SWIZZLE_NONE		0
 #define I915_BIT_6_SWIZZLE_9		1
-- 
2.24.1.485.gad05a3d8e5


^ permalink raw reply related	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2021-09-29  6:15 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-23  8:48 [Intel-gfx] [PATCH] drm/i915: Tile F plane format support Stanislav Lisovskiy
2021-09-23  9:20 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-09-23  9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-23 10:28 ` [Intel-gfx] [PATCH] " Jani Nikula
2021-09-23 10:44   ` Lisovskiy, Stanislav
2021-09-23 11:51     ` Lisovskiy, Stanislav
2021-09-23 11:03 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
2021-09-23 15:49 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2021-09-23 16:19   ` Lisovskiy, Stanislav
2021-09-27 18:23   ` Matt Roper
2021-09-27 18:29     ` Ville Syrjälä
2021-09-28  5:24       ` Matt Roper
2021-09-28 12:49         ` Lisovskiy, Stanislav
2021-09-28 19:02           ` Ville Syrjälä
2021-09-28 20:36             ` Lisovskiy, Stanislav
2021-09-28 20:47               ` Ville Syrjälä
2021-09-29  6:15                 ` Lisovskiy, Stanislav
2021-09-23 13:17 Stanislav Lisovskiy

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