From: Tom Rini <trini@konsulko.com>
To: "Pali Rohár" <pali@kernel.org>
Cc: Simon Glass <sjg@chromium.org>, Stefan Roese <sr@denx.de>,
Phil Sutter <phil@nwl.cc>,
u-boot@lists.denx.de
Subject: Re: [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges
Date: Thu, 23 Sep 2021 22:41:37 -0400 [thread overview]
Message-ID: <20210924024137.GM31748@bill-the-cat> (raw)
In-Reply-To: <20210910113335.8283-1-pali@kernel.org>
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On Fri, Sep 10, 2021 at 01:33:35PM +0200, Pali Rohár wrote:
> Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
> and should be zero. So do not set them to non-zero value.
>
> Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
> contain information if 64-bit memory addressing is supported. So preserve
> this information when overwriting these registers.
>
> Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
> if 32-bit io addressing is supported. So preserve this information and do
> not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
> PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Reviewed-by: Stefan Roese <sr@denx.de>
Applied to u-boot/next, thanks!
--
Tom
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prev parent reply other threads:[~2021-09-24 2:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-10 11:33 [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges Pali Rohár
2021-09-20 5:44 ` Stefan Roese
2021-09-24 2:41 ` Tom Rini [this message]
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