From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70BAEC433EF for ; Fri, 24 Sep 2021 10:31:24 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id E84A6610CB for ; Fri, 24 Sep 2021 10:31:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org E84A6610CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5283E41300; Fri, 24 Sep 2021 12:31:23 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id D053640142 for ; Fri, 24 Sep 2021 12:31:18 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10116"; a="211285636" X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="211285636" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Sep 2021 03:31:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,319,1624345200"; d="scan'208";a="653983541" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 24 Sep 2021 03:31:16 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Fri, 24 Sep 2021 11:31:13 +0100 Message-Id: <20210924103113.2878126-1-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210924102942.2878051-1-bruce.richardson@intel.com> References: <20210924102942.2878051-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v6 10/13] dmadev: add flag for error handling support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Due to HW or driver limiations, not all dmadevs may support full error handling e.g. safely managing and reporting an invalid address to a copy operation. The skeleton dmadev, for example, being pure software will always seg-fault if passed an invalid address. To indicate the availability of safe error handling by a device, we add a capability flag for it. Signed-off-by: Bruce Richardson --- lib/dmadev/rte_dmadev.c | 1 + lib/dmadev/rte_dmadev.h | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/lib/dmadev/rte_dmadev.c b/lib/dmadev/rte_dmadev.c index a761fe1a91..c9224035dc 100644 --- a/lib/dmadev/rte_dmadev.c +++ b/lib/dmadev/rte_dmadev.c @@ -665,6 +665,7 @@ dma_capability_name(uint64_t capability) { RTE_DMA_CAPA_DEV_TO_DEV, "dev2dev" }, { RTE_DMA_CAPA_SVA, "sva" }, { RTE_DMA_CAPA_SILENT, "silent" }, + { RTE_DMA_CAPA_HANDLES_ERRORS, "handles_errors" }, { RTE_DMA_CAPA_OPS_COPY, "copy" }, { RTE_DMA_CAPA_OPS_COPY_SG, "copy_sg" }, { RTE_DMA_CAPA_OPS_FILL, "fill" }, diff --git a/lib/dmadev/rte_dmadev.h b/lib/dmadev/rte_dmadev.h index 04565f8c5b..ae0b357343 100644 --- a/lib/dmadev/rte_dmadev.h +++ b/lib/dmadev/rte_dmadev.h @@ -273,6 +273,15 @@ int16_t rte_dma_next_dev(int16_t start_dev_id); * @see struct rte_dma_conf::silent_mode */ #define RTE_DMA_CAPA_SILENT RTE_BIT64(5) +/** DMA device supports error handling + * + * With this bit set, invalid input addresses will be reported as operation failures + * to the user but other operations can continue. + * Without this bit set, invalid data is not handled by either HW or driver, so user + * must ensure that all memory addresses are valid and accessible by HW. + */ +#define RTE_DMA_CAPA_HANDLES_ERRORS RTE_BIT64(6) + /** DMA device support copy ops. * This capability start with index of 32, so that it could leave gap between * normal capability and ops capability. -- 2.30.2